Wealian Liao de3fccdd64 dts: arm: npcx: Add PSL_IN3/4 for initial pin config ... PSL_IN pin select register is Vsby power-up reset. When the other core-domain-reset reset the chip, PSL_IN3/4 don't set to GPIO. This commit adds PSL_IN3/4 to the pin select list in NPCX devicetree. So these pins can be set to GPIO when the other core-domain-reset. Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>		2021-12-13 20:37:28 -05:00
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npcx	dts: npcx: add device-tree files of npcx9 series.	2021-06-04 16:14:48 -05:00
m48x.dtsi	soc: arm: rename soc/arm/nuvoton as soc/arm/nuvoton_numicro	2021-08-07 20:37:24 -04:00
npcx7.dtsi	dts: arm: npcx: Add PSL_IN3/4 for initial pin config	2021-12-13 20:37:28 -05:00
npcx7m6fb.dtsi	drivers: spi: npcx: add SPI support to access the SPI flash	2021-11-01 21:48:20 -04:00
npcx7m6fc.dtsi	drivers: spi: npcx: add SPI support to access the SPI flash	2021-11-01 21:48:20 -04:00
npcx7m7fc.dtsi	drivers: spi: npcx: add SPI support to access the SPI flash	2021-11-01 21:48:20 -04:00
npcx9.dtsi	dts: arm: npcx: Add PSL_IN3/4 for initial pin config	2021-12-13 20:37:28 -05:00
npcx9m3f.dtsi	drivers: spi: npcx: add SPI support to access the SPI flash	2021-11-01 21:48:20 -04:00
npcx9m6f.dtsi	drivers: spi: npcx: add SPI support to access the SPI flash	2021-11-01 21:48:20 -04:00
npcx.dtsi	drivers: spi: npcx: add SPI support to access the SPI flash	2021-11-01 21:48:20 -04:00