e70907f52d
Program flow will behave incorrectly (memory and instruction fetches return invalid data) if Flexspi is accessed by the Flexspi driver while being used as XIP memory by the Cortex M7. Set logging to disabled by when XIP mode is used in the memc and flexspi drivers, and warn the user if they attempt to enable it. Fixes #40133 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
684 lines
20 KiB
C
684 lines
20 KiB
C
/*
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* Copyright (c) 2021 Volvo Construction Equipment
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_imx_flexspi_hyperflash
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#include <zephyr.h>
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#include <errno.h>
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#include <drivers/flash.h>
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#include <logging/log.h>
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/*
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* NOTE: If CONFIG_FLASH_MCUX_FLEXSPI_XIP is selected, Any external functions
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* called while interacting with the flexspi MUST be relocated to SRAM or ITCM
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* at runtime, so that the chip does not access the flexspi to read program
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* instructions while it is being written to
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*/
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#if defined(CONFIG_FLASH_MCUX_FLEXSPI_XIP) && (CONFIG_FLASH_LOG_LEVEL > 0)
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#warning "Enabling flash driver logging and XIP mode simultaneously can cause \
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read-while-write hazards. This configuration is not recommended."
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#endif
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LOG_MODULE_REGISTER(flexspi_hyperflash, CONFIG_FLASH_LOG_LEVEL);
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#ifdef CONFIG_HAS_MCUX_CACHE
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#include <fsl_cache.h>
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#endif
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#include <sys/util.h>
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#include "memc_mcux_flexspi.h"
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#define SPI_HYPERFLASH_SECTOR_SIZE (0x40000U)
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#define SPI_HYPERFLASH_PAGE_SIZE (512U)
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#define HYPERFLASH_WRITE_SIZE (16)
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#define HYPERFLASH_ERASE_VALUE (0xFF)
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#ifdef CONFIG_FLASH_MCUX_FLEXSPI_HYPERFLASH_WRITE_BUFFER
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static uint8_t hyperflash_write_buf[SPI_HYPERFLASH_PAGE_SIZE];
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#endif
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enum {
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/* Instructions matching with XIP layout */
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READ_DATA = 0,
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WRITE_DATA = 1,
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READ_STATUS = 2,
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WRITE_ENABLE = 4,
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ERASE_SECTOR = 6,
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PAGE_PROGRAM = 10,
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ERASE_CHIP = 12,
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};
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#define CUSTOM_LUT_LENGTH 64
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static const uint32_t flash_flexspi_hyperflash_lut[CUSTOM_LUT_LENGTH] = {
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/* Read Data */
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[4 * READ_DATA] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0,
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kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
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[4 * READ_DATA + 1] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10,
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kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04),
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/* Write Data */
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[4 * WRITE_DATA] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
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[4 * WRITE_DATA + 1] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10,
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kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x02),
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/* Read Status */
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[4 * READ_STATUS] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * READ_STATUS + 1] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
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[4 * READ_STATUS + 2] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
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[4 * READ_STATUS + 3] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x70),
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[4 * READ_STATUS + 4] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0,
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kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
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[4 * READ_STATUS + 5] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10,
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kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x0B),
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[4 * READ_STATUS + 6] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
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/* Write Enable */
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[4 * WRITE_ENABLE] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * WRITE_ENABLE + 1] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
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[4 * WRITE_ENABLE + 2] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
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[4 * WRITE_ENABLE + 3] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
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[4 * WRITE_ENABLE + 4] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * WRITE_ENABLE + 5] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
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[4 * WRITE_ENABLE + 6] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
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[4 * WRITE_ENABLE + 7] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
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/* Erase Sector */
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[4 * ERASE_SECTOR] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * ERASE_SECTOR + 1] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
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[4 * ERASE_SECTOR + 2] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
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[4 * ERASE_SECTOR + 3] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80),
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[4 * ERASE_SECTOR + 4] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * ERASE_SECTOR + 5] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
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[4 * ERASE_SECTOR + 6] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
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[4 * ERASE_SECTOR + 7] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
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[4 * ERASE_SECTOR + 8] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * ERASE_SECTOR + 9] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
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[4 * ERASE_SECTOR + 10] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
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[4 * ERASE_SECTOR + 11] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
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[4 * ERASE_SECTOR + 12] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
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[4 * ERASE_SECTOR + 13] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * ERASE_SECTOR + 14] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
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/* program page with word program command sequence */
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[4 * PAGE_PROGRAM] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * PAGE_PROGRAM + 1] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
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[4 * PAGE_PROGRAM + 2] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
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[4 * PAGE_PROGRAM + 3] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0),
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[4 * PAGE_PROGRAM + 4] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
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[4 * PAGE_PROGRAM + 5] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10,
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kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x80),
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/* Erase chip */
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[4 * ERASE_CHIP] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * ERASE_CHIP + 1] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
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[4 * ERASE_CHIP + 2] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
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[4 * ERASE_CHIP + 3] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80),
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/* 1 */
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[4 * ERASE_CHIP + 4] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * ERASE_CHIP + 5] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
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[4 * ERASE_CHIP + 6] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
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[4 * ERASE_CHIP + 7] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
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/* 2 */
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[4 * ERASE_CHIP + 8] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * ERASE_CHIP + 9] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
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[4 * ERASE_CHIP + 10] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
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[4 * ERASE_CHIP + 11] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
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/* 3 */
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[4 * ERASE_CHIP + 12] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * ERASE_CHIP + 13] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
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[4 * ERASE_CHIP + 14] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
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[4 * ERASE_CHIP + 15] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x10),
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};
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struct flash_flexspi_hyperflash_config {
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char *controller_label;
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flexspi_port_t port;
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flexspi_device_config_t config;
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struct flash_pages_layout layout;
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struct flash_parameters flash_parameters;
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};
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struct flash_flexspi_hyperflash_data {
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const struct device *controller;
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};
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static int flash_flexspi_hyperflash_wait_bus_busy(const struct device *dev)
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{
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const struct flash_flexspi_hyperflash_config *config = dev->config;
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struct flash_flexspi_hyperflash_data *data = dev->data;
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flexspi_transfer_t transfer;
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int ret;
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bool is_busy;
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uint32_t read_value;
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transfer.deviceAddress = 0;
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transfer.port = config->port;
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transfer.cmdType = kFLEXSPI_Read;
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transfer.SeqNumber = 2;
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transfer.seqIndex = READ_STATUS;
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transfer.data = &read_value;
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transfer.dataSize = 2;
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do {
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ret = memc_flexspi_transfer(data->controller, &transfer);
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if (ret != 0) {
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return ret;
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}
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is_busy = !(read_value & 0x8000);
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if (read_value & 0x3200) {
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ret = -EINVAL;
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break;
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}
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} while (is_busy);
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return ret;
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}
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static int flash_flexspi_hyperflash_write_enable(const struct device *dev, uint32_t address)
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{
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const struct flash_flexspi_hyperflash_config *config = dev->config;
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struct flash_flexspi_hyperflash_data *data = dev->data;
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flexspi_transfer_t transfer;
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int ret;
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transfer.deviceAddress = address;
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transfer.port = config->port;
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transfer.cmdType = kFLEXSPI_Command;
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transfer.SeqNumber = 2;
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transfer.seqIndex = WRITE_ENABLE;
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ret = memc_flexspi_transfer(data->controller, &transfer);
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return ret;
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}
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static int flash_flexspi_hyperflash_check_vendor_id(const struct device *dev)
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{
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const struct flash_flexspi_hyperflash_config *config = dev->config;
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struct flash_flexspi_hyperflash_data *data = dev->data;
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uint8_t writebuf[4] = {0x00, 0x98};
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uint32_t buffer[2];
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int ret;
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flexspi_transfer_t transfer;
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transfer.deviceAddress = (0x555 * 2);
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transfer.port = config->port;
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transfer.cmdType = kFLEXSPI_Write;
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transfer.SeqNumber = 1;
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transfer.seqIndex = WRITE_DATA;
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transfer.data = (uint32_t *)writebuf;
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transfer.dataSize = 2;
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LOG_DBG("Reading id");
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ret = memc_flexspi_transfer(data->controller, &transfer);
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if (ret != 0) {
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LOG_ERR("failed to CFI");
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return ret;
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}
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transfer.deviceAddress = (0x10 * 2);
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transfer.port = config->port;
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transfer.cmdType = kFLEXSPI_Read;
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transfer.SeqNumber = 1;
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transfer.seqIndex = READ_DATA;
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transfer.data = buffer;
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transfer.dataSize = 8;
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ret = memc_flexspi_transfer(data->controller, &transfer);
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if (ret != 0) {
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LOG_ERR("failed to read id");
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return ret;
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}
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buffer[1] &= 0xFFFF;
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/* Check that the data read out is unicode "QRY" in big-endian order */
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if ((buffer[0] != 0x52005100) || (buffer[1] != 0x5900)) {
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LOG_ERR("data read out is wrong!");
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return -EINVAL;
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}
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writebuf[1] = 0xF0;
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transfer.deviceAddress = 0;
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transfer.port = config->port;
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transfer.cmdType = kFLEXSPI_Write;
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transfer.SeqNumber = 1;
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transfer.seqIndex = WRITE_DATA;
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transfer.data = (uint32_t *)writebuf;
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transfer.dataSize = 2;
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ret = memc_flexspi_transfer(data->controller, &transfer);
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if (ret != 0) {
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LOG_ERR("failed to exit");
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return ret;
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}
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memc_flexspi_reset(data->controller);
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return ret;
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}
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static int flash_flexspi_hyperflash_page_program(const struct device *dev, off_t
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offset, const void *buffer, size_t len)
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{
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const struct flash_flexspi_hyperflash_config *config = dev->config;
|
|
struct flash_flexspi_hyperflash_data *data = dev->data;
|
|
flexspi_transfer_t transfer = {
|
|
.deviceAddress = offset,
|
|
.port = config->port,
|
|
.cmdType = kFLEXSPI_Write,
|
|
.SeqNumber = 2,
|
|
.seqIndex = PAGE_PROGRAM,
|
|
.data = (uint32_t *)buffer,
|
|
.dataSize = len,
|
|
};
|
|
|
|
LOG_DBG("Page programming %d bytes to 0x%08x", len, offset);
|
|
|
|
return memc_flexspi_transfer(data->controller, &transfer);
|
|
}
|
|
|
|
static int flash_flexspi_hyperflash_read(const struct device *dev, off_t offset,
|
|
void *buffer, size_t len)
|
|
{
|
|
const struct flash_flexspi_hyperflash_config *config = dev->config;
|
|
struct flash_flexspi_hyperflash_data *data = dev->data;
|
|
uint8_t *src = memc_flexspi_get_ahb_address(data->controller,
|
|
config->port,
|
|
offset);
|
|
if (!src) {
|
|
return -EINVAL;
|
|
}
|
|
|
|
memcpy(buffer, src, len);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int flash_flexspi_hyperflash_write(const struct device *dev, off_t offset,
|
|
const void *buffer, size_t len)
|
|
{
|
|
const struct flash_flexspi_hyperflash_config *config = dev->config;
|
|
struct flash_flexspi_hyperflash_data *data = dev->data;
|
|
size_t size = len;
|
|
uint8_t *src = (uint8_t *)buffer;
|
|
unsigned int key = 0;
|
|
int i;
|
|
int ret = -1;
|
|
|
|
uint8_t *dst = memc_flexspi_get_ahb_address(data->controller,
|
|
config->port,
|
|
offset);
|
|
if (!dst) {
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (memc_flexspi_is_running_xip(data->controller)) {
|
|
key = irq_lock();
|
|
}
|
|
|
|
while (len) {
|
|
/* Writing between two page sizes crashes the platform so we
|
|
* have to write the part that fits in the first page and then
|
|
* update the offset.
|
|
*/
|
|
i = MIN(SPI_HYPERFLASH_PAGE_SIZE - (offset %
|
|
SPI_HYPERFLASH_PAGE_SIZE), len);
|
|
#ifdef CONFIG_FLASH_MCUX_FLEXSPI_HYPERFLASH_WRITE_BUFFER
|
|
memcpy(hyperflash_write_buf, src, i);
|
|
#endif
|
|
ret = flash_flexspi_hyperflash_write_enable(dev, offset);
|
|
if (ret != 0) {
|
|
LOG_ERR("failed to enable write");
|
|
break;
|
|
}
|
|
#ifdef CONFIG_FLASH_MCUX_FLEXSPI_HYPERFLASH_WRITE_BUFFER
|
|
ret = flash_flexspi_hyperflash_page_program(dev, offset,
|
|
hyperflash_write_buf, i);
|
|
#else
|
|
ret = flash_flexspi_hyperflash_page_program(dev, offset, src, i);
|
|
#endif
|
|
if (ret != 0) {
|
|
LOG_ERR("failed to write");
|
|
break;
|
|
}
|
|
|
|
ret = flash_flexspi_hyperflash_wait_bus_busy(dev);
|
|
if (ret != 0) {
|
|
LOG_ERR("failed to wait bus busy");
|
|
break;
|
|
}
|
|
|
|
/* Do software reset. */
|
|
memc_flexspi_reset(data->controller);
|
|
src += i;
|
|
offset += i;
|
|
len -= i;
|
|
}
|
|
|
|
if (memc_flexspi_is_running_xip(data->controller)) {
|
|
irq_unlock(key);
|
|
}
|
|
|
|
#ifdef CONFIG_HAS_MCUX_CACHE
|
|
DCACHE_InvalidateByRange((uint32_t) dst, size);
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int flash_flexspi_hyperflash_erase(const struct device *dev, off_t offset, size_t size)
|
|
{
|
|
const struct flash_flexspi_hyperflash_config *config = dev->config;
|
|
struct flash_flexspi_hyperflash_data *data = dev->data;
|
|
flexspi_transfer_t transfer;
|
|
int ret = -1;
|
|
int i;
|
|
unsigned int key = 0;
|
|
int num_sectors = size / SPI_HYPERFLASH_SECTOR_SIZE;
|
|
uint8_t *dst = memc_flexspi_get_ahb_address(data->controller,
|
|
config->port,
|
|
offset);
|
|
|
|
if (!dst) {
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (offset % SPI_HYPERFLASH_SECTOR_SIZE) {
|
|
LOG_ERR("Invalid offset");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (size % SPI_HYPERFLASH_SECTOR_SIZE) {
|
|
LOG_ERR("Invalid offset");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (memc_flexspi_is_running_xip(data->controller)) {
|
|
key = irq_lock();
|
|
}
|
|
|
|
for (i = 0; i < num_sectors; i++) {
|
|
ret = flash_flexspi_hyperflash_write_enable(dev, offset);
|
|
if (ret != 0) {
|
|
LOG_ERR("failed to write_enable");
|
|
break;
|
|
}
|
|
|
|
LOG_DBG("Erasing sector at 0x%08x", offset);
|
|
|
|
transfer.deviceAddress = offset;
|
|
transfer.port = config->port;
|
|
transfer.cmdType = kFLEXSPI_Command;
|
|
transfer.SeqNumber = 4;
|
|
transfer.seqIndex = ERASE_SECTOR;
|
|
|
|
ret = memc_flexspi_transfer(data->controller, &transfer);
|
|
if (ret != 0) {
|
|
LOG_ERR("failed to erase");
|
|
break;
|
|
}
|
|
|
|
/* wait bus busy */
|
|
ret = flash_flexspi_hyperflash_wait_bus_busy(dev);
|
|
if (ret != 0) {
|
|
LOG_ERR("failed to wait bus busy");
|
|
break;
|
|
}
|
|
|
|
/* Do software reset. */
|
|
memc_flexspi_reset(data->controller);
|
|
|
|
offset += SPI_HYPERFLASH_SECTOR_SIZE;
|
|
}
|
|
|
|
if (memc_flexspi_is_running_xip(data->controller)) {
|
|
irq_unlock(key);
|
|
}
|
|
|
|
#ifdef CONFIG_HAS_MCUX_CACHE
|
|
DCACHE_InvalidateByRange((uint32_t) dst, size);
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct flash_parameters *flash_flexspi_hyperflash_get_parameters(
|
|
const struct device *dev)
|
|
{
|
|
const struct flash_flexspi_hyperflash_config *config = dev->config;
|
|
|
|
return &config->flash_parameters;
|
|
}
|
|
|
|
|
|
static void flash_flexspi_hyperflash_pages_layout(const struct device *dev,
|
|
const struct flash_pages_layout **layout,
|
|
size_t *layout_size)
|
|
{
|
|
const struct flash_flexspi_hyperflash_config *config = dev->config;
|
|
|
|
*layout = &config->layout;
|
|
*layout_size = 1;
|
|
}
|
|
|
|
static int flash_flexspi_hyperflash_init(const struct device *dev)
|
|
{
|
|
const struct flash_flexspi_hyperflash_config *config = dev->config;
|
|
struct flash_flexspi_hyperflash_data *data = dev->data;
|
|
|
|
data->controller = device_get_binding(config->controller_label);
|
|
if (data->controller == NULL) {
|
|
LOG_ERR("Could not find controller");
|
|
return -EINVAL;
|
|
}
|
|
|
|
memc_flexspi_wait_bus_idle(data->controller);
|
|
|
|
if (memc_flexspi_set_device_config(data->controller, &config->config,
|
|
config->port)) {
|
|
LOG_ERR("Could not set device configuration");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (memc_flexspi_update_lut(data->controller, 0,
|
|
(const uint32_t *) flash_flexspi_hyperflash_lut,
|
|
sizeof(flash_flexspi_hyperflash_lut)/4)) {
|
|
LOG_ERR("Could not update lut");
|
|
return -EINVAL;
|
|
}
|
|
|
|
memc_flexspi_reset(data->controller);
|
|
|
|
if (flash_flexspi_hyperflash_check_vendor_id(dev)) {
|
|
LOG_ERR("Could not read vendor id");
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct flash_driver_api flash_flexspi_hyperflash_api = {
|
|
.read = flash_flexspi_hyperflash_read,
|
|
.write = flash_flexspi_hyperflash_write,
|
|
.erase = flash_flexspi_hyperflash_erase,
|
|
.get_parameters = flash_flexspi_hyperflash_get_parameters,
|
|
#if defined(CONFIG_FLASH_PAGE_LAYOUT)
|
|
.page_layout = flash_flexspi_hyperflash_pages_layout,
|
|
#endif
|
|
};
|
|
|
|
#define CONCAT3(x, y, z) x ## y ## z
|
|
|
|
#define CS_INTERVAL_UNIT(unit) \
|
|
CONCAT3(kFLEXSPI_CsIntervalUnit, unit, SckCycle)
|
|
|
|
#define AHB_WRITE_WAIT_UNIT(unit) \
|
|
CONCAT3(kFLEXSPI_AhbWriteWaitUnit, unit, AhbCycle)
|
|
|
|
#define FLASH_FLEXSPI_DEVICE_CONFIG(n) \
|
|
{ \
|
|
.flexspiRootClk = MHZ(42), \
|
|
.flashSize = DT_INST_PROP(n, size) / 8 / KB(1), \
|
|
.CSIntervalUnit = \
|
|
CS_INTERVAL_UNIT( \
|
|
DT_INST_PROP(n, cs_interval_unit)), \
|
|
.CSInterval = DT_INST_PROP(n, cs_interval), \
|
|
.CSHoldTime = DT_INST_PROP(n, cs_hold_time), \
|
|
.CSSetupTime = DT_INST_PROP(n, cs_setup_time), \
|
|
.dataValidTime = DT_INST_PROP(n, data_valid_time), \
|
|
.columnspace = DT_INST_PROP(n, column_space), \
|
|
.enableWordAddress = DT_INST_PROP(n, word_addressable), \
|
|
.AWRSeqIndex = WRITE_DATA, \
|
|
.AWRSeqNumber = 1, \
|
|
.ARDSeqIndex = READ_DATA, \
|
|
.ARDSeqNumber = 1, \
|
|
.AHBWriteWaitUnit = \
|
|
AHB_WRITE_WAIT_UNIT( \
|
|
DT_INST_PROP(n, ahb_write_wait_unit)), \
|
|
.AHBWriteWaitInterval = \
|
|
DT_INST_PROP(n, ahb_write_wait_interval), \
|
|
} \
|
|
|
|
#define FLASH_FLEXSPI_HYPERFLASH(n) \
|
|
static const struct flash_flexspi_hyperflash_config \
|
|
flash_flexspi_hyperflash_config_##n = { \
|
|
.controller_label = DT_INST_BUS_LABEL(n), \
|
|
.port = DT_INST_REG_ADDR(n), \
|
|
.config = FLASH_FLEXSPI_DEVICE_CONFIG(n), \
|
|
.layout = { \
|
|
.pages_count = DT_INST_PROP(n, size) / 8 \
|
|
/ SPI_HYPERFLASH_SECTOR_SIZE, \
|
|
.pages_size = SPI_HYPERFLASH_SECTOR_SIZE, \
|
|
}, \
|
|
.flash_parameters = { \
|
|
.write_block_size = HYPERFLASH_WRITE_SIZE, \
|
|
.erase_value = HYPERFLASH_ERASE_VALUE, \
|
|
}, \
|
|
}; \
|
|
\
|
|
static struct flash_flexspi_hyperflash_data \
|
|
flash_flexspi_hyperflash_data_##n; \
|
|
\
|
|
DEVICE_DT_INST_DEFINE(n, \
|
|
flash_flexspi_hyperflash_init, \
|
|
NULL, \
|
|
&flash_flexspi_hyperflash_data_##n, \
|
|
&flash_flexspi_hyperflash_config_##n, \
|
|
POST_KERNEL, \
|
|
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
|
|
&flash_flexspi_hyperflash_api);
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(FLASH_FLEXSPI_HYPERFLASH)
|