Flavio Ceolin 7dd4297214 pm: Remove unused parameter ... The number of ticks on z_pm_save_idle_exit is not used and there is no need to have it. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>		2021-11-17 11:15:49 -05:00
..
mpu	arch: arc: add support of mpu v6	2021-08-27 11:45:43 -04:00
offsets	ARC: allow to build code for processors without ZOL	2021-05-07 14:55:49 -05:00
secureshield
arc_connect.c
arc_smp.c	arch: arc: update ARConnect ICD select mask when new cpu come online	2021-07-06 15:10:39 -05:00
cache.c	cache: Rename sys_{dcache,icache}_* to sys_{data,instr}_cache_*	2021-05-08 07:00:33 +02:00
CMakeLists.txt	cmake: Support coverage flags on all archs	2021-06-10 18:01:36 -04:00
cpu_idle.S	ARC: rewrite ASM code with asm-compat macroses	2021-05-07 14:55:49 -05:00
fast_irq.S
fatal.c	ARC: allow to build code for processors without ZOL	2021-05-07 14:55:49 -05:00
fault_s.S	ARC: rewrite ASM code with asm-compat macroses	2021-05-07 14:55:49 -05:00
fault.c
irq_manage.c
irq_offload.c
isr_wrapper.S	pm: Remove unused parameter	2021-11-17 11:15:49 -05:00
prep_c.c
regular_irq.S	ARC: allow to build code for processors without ZOL	2021-05-07 14:55:49 -05:00
reset.S	ARC: ARCv3 64: adopt ARC SMP code for ARCv3 64 bit	2021-08-07 20:36:23 -04:00
switch.S	ARC: mark accesses which are 32 bit despite of platform bittnes	2021-05-07 14:55:49 -05:00
thread_entry_wrapper.S	ARC: rewrite ASM code with asm-compat macroses	2021-05-07 14:55:49 -05:00
thread.c	ARC: add TLS support for ARCv3	2021-05-07 14:55:49 -05:00
timestamp.c
tls.c
userspace.S
vector_table.c	ARC: make vector table bit agnostic	2021-05-07 14:55:49 -05:00
vector_table.ld