4344e27c26
Update reserved function names starting with one underscore, replacing them as follows: '_k_' with 'z_' '_K_' with 'Z_' '_handler_' with 'z_handl_' '_Cstart' with 'z_cstart' '_Swap' with 'z_swap' This renaming is done on both global and those static function names in kernel/include and include/. Other static function names in kernel/ are renamed by removing the leading underscore. Other function names not starting with any prefix listed above are renamed starting with a 'z_' or 'Z_' prefix. Function names starting with two or three leading underscores are not automatcally renamed since these names will collide with the variants with two or three leading underscores. Various generator scripts have also been updated as well as perf, linker and usb files. These are drivers/serial/uart_handlers.c include/linker/kobject-text.ld kernel/include/syscall_handler.h scripts/gen_kobject_list.py scripts/gen_syscall_header.py Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
319 lines
5.7 KiB
C
319 lines
5.7 KiB
C
/* asm_inline_gcc.h - ARC inline assembler and macros for public functions */
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_ASM_INLINE_GCC_H_
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#define ZEPHYR_INCLUDE_ARCH_ARC_V2_ASM_INLINE_GCC_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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#include <sys_io.h>
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#include <arch/arc/v2/aux_regs.h>
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#include <zephyr/types.h>
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#include <stddef.h>
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/**
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* @brief read timestamp register (CPU frequency)
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*/
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extern u64_t z_tsc_read(void);
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/* Implementation of sys_io.h's documented functions */
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static ALWAYS_INLINE
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void sys_out8(u8_t data, io_port_t port)
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{
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z_arc_v2_aux_reg_write(port, data);
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}
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static ALWAYS_INLINE
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u8_t sys_in8(io_port_t port)
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{
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return (u8_t)(z_arc_v2_aux_reg_read(port) & 0x000000ff);
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}
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static ALWAYS_INLINE
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void sys_out16(u16_t data, io_port_t port)
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{
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z_arc_v2_aux_reg_write(port, data);
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}
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static ALWAYS_INLINE
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u16_t sys_in16(io_port_t port)
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{
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return (u16_t)(z_arc_v2_aux_reg_read(port) & 0x0000ffff);
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}
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static ALWAYS_INLINE
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void sys_out32(u32_t data, io_port_t port)
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{
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z_arc_v2_aux_reg_write(port, data);
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}
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static ALWAYS_INLINE
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u32_t sys_in32(io_port_t port)
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{
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return z_arc_v2_aux_reg_read(port);
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}
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static ALWAYS_INLINE
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void sys_io_set_bit(io_port_t port, unsigned int bit)
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{
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u32_t reg = 0;
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__asm__ volatile("lr %1, [%0]\n"
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"bset %1, %1, %2\n"
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"sr %1, [%0];\n\t"
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:
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: "ir" (port),
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"r" (reg), "Mr" (bit)
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: "memory", "cc");
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}
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static ALWAYS_INLINE
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void sys_io_clear_bit(io_port_t port, unsigned int bit)
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{
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u32_t reg = 0;
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__asm__ volatile("lr %1, [%0]\n"
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"bclr %1, %1, %2\n"
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"sr %1, [%0];\n\t"
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:
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: "ir" (port),
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"r" (reg), "Mr" (bit)
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: "memory", "cc");
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}
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static ALWAYS_INLINE
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int sys_io_test_bit(io_port_t port, unsigned int bit)
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{
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u32_t status = _ARC_V2_STATUS32;
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u32_t reg = 0;
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u32_t ret;
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__asm__ volatile("lr %2, [%1]\n"
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"btst %2, %3\n"
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"lr %0, [%4];\n\t"
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: "=r" (ret)
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: "ir" (port),
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"r" (reg), "Mr" (bit), "i" (status)
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: "memory", "cc");
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return !(ret & _ARC_V2_STATUS32_Z);
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}
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static ALWAYS_INLINE
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int sys_io_test_and_set_bit(io_port_t port, unsigned int bit)
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{
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int ret;
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ret = sys_io_test_bit(port, bit);
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sys_io_set_bit(port, bit);
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return ret;
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}
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static ALWAYS_INLINE
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int sys_io_test_and_clear_bit(io_port_t port, unsigned int bit)
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{
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int ret;
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ret = sys_io_test_bit(port, bit);
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sys_io_clear_bit(port, bit);
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return ret;
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}
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static ALWAYS_INLINE
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void sys_write8(u8_t data, mm_reg_t addr)
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{
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__asm__ volatile("stb%U1 %0, %1;\n\t"
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:
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: "r" (data), "m" (*(volatile u8_t *) addr)
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: "memory");
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}
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static ALWAYS_INLINE
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u8_t sys_read8(mm_reg_t addr)
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{
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u8_t ret;
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__asm__ volatile("ldb%U1 %0, %1;\n\t"
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: "=r" (ret)
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: "m" (*(volatile u8_t *) addr)
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: "memory");
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return ret;
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}
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static ALWAYS_INLINE
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void sys_write16(u16_t data, mm_reg_t addr)
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{
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__asm__ volatile("sth%U1 %0, %1;\n\t"
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:
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: "r" (data), "m" (*(volatile u16_t *) addr)
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: "memory");
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}
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static ALWAYS_INLINE
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u16_t sys_read16(mm_reg_t addr)
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{
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u16_t ret;
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__asm__ volatile("ldh%U1 %0, %1;\n\t"
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: "=r" (ret)
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: "m" (*(volatile u16_t *) addr)
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: "memory");
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return ret;
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}
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static ALWAYS_INLINE
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void sys_write32(u32_t data, mm_reg_t addr)
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{
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__asm__ volatile("st%U1 %0, %1;\n\t"
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:
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: "r" (data), "m" (*(volatile u32_t *) addr)
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: "memory");
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}
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static ALWAYS_INLINE
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u32_t sys_read32(mm_reg_t addr)
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{
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u32_t ret;
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__asm__ volatile("ld%U1 %0, %1;\n\t"
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: "=r" (ret)
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: "m" (*(volatile u32_t *) addr)
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: "memory");
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return ret;
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}
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static ALWAYS_INLINE
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void sys_set_bit(mem_addr_t addr, unsigned int bit)
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{
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u32_t reg = 0;
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__asm__ volatile("ld %1, %0\n"
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"bset %1, %1, %2\n"
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"st %1, %0;\n\t"
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: "+m" (*(volatile u32_t *) addr)
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: "r" (reg), "Mr" (bit)
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: "memory", "cc");
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}
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static ALWAYS_INLINE
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void sys_clear_bit(mem_addr_t addr, unsigned int bit)
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{
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u32_t reg = 0;
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__asm__ volatile("ld %1, %0\n"
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"bclr %1, %1, %2\n"
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"st %1, %0;\n\t"
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: "+m" (*(volatile u32_t *) addr)
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: "r" (reg), "Mr" (bit)
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: "memory", "cc");
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}
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static ALWAYS_INLINE
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int sys_test_bit(mem_addr_t addr, unsigned int bit)
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{
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u32_t status = _ARC_V2_STATUS32;
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u32_t reg = 0;
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u32_t ret;
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__asm__ volatile("ld %2, %1\n"
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"btst %2, %3\n"
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"lr %0, [%4];\n\t"
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: "=r" (ret)
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: "m" (*(volatile u32_t *) addr),
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"r" (reg), "Mr" (bit), "i" (status)
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: "memory", "cc");
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return !(ret & _ARC_V2_STATUS32_Z);
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}
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static ALWAYS_INLINE
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int sys_test_and_set_bit(mem_addr_t addr, unsigned int bit)
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{
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int ret;
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ret = sys_test_bit(addr, bit);
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sys_set_bit(addr, bit);
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return ret;
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}
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static ALWAYS_INLINE
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int sys_test_and_clear_bit(mem_addr_t addr, unsigned int bit)
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{
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int ret;
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ret = sys_test_bit(addr, bit);
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sys_clear_bit(addr, bit);
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return ret;
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}
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static ALWAYS_INLINE
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void sys_bitfield_set_bit(mem_addr_t addr, unsigned int bit)
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{
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/* Doing memory offsets in terms of 32-bit values to prevent
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* alignment issues
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*/
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sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
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}
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static ALWAYS_INLINE
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void sys_bitfield_clear_bit(mem_addr_t addr, unsigned int bit)
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{
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sys_clear_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
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}
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static ALWAYS_INLINE
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int sys_bitfield_test_bit(mem_addr_t addr, unsigned int bit)
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{
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return sys_test_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
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}
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static ALWAYS_INLINE
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int sys_bitfield_test_and_set_bit(mem_addr_t addr, unsigned int bit)
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{
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int ret;
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ret = sys_bitfield_test_bit(addr, bit);
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sys_bitfield_set_bit(addr, bit);
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return ret;
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}
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static ALWAYS_INLINE
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int sys_bitfield_test_and_clear_bit(mem_addr_t addr, unsigned int bit)
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{
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int ret;
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ret = sys_bitfield_test_bit(addr, bit);
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sys_bitfield_clear_bit(addr, bit);
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return ret;
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}
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_INCLUDE_ARCH_ARC_V2_ASM_INLINE_GCC_H_ */
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