zephyr/drivers/clock_control/clock_stm32f7x.c
Yaël Boutreux f6343ace8e drivers: clock_control: stm32: Modify file naming pattern
Change file naming pattern from BoardNameX_ll_clock.c to
clock_BoardNameX.c
File containing LL functions will have the "_ll_" naming
scheme (such as clock_stm32_ll_common.c and .h)

Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-26 02:56:20 -07:00

51 lines
1.1 KiB
C

/*
* Copyright (c) 2018 Yurii Hamann
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <soc_registers.h>
#include <clock_control.h>
#include <misc/util.h>
#include <clock_control/stm32_clock_control.h>
#include "clock_stm32_ll_common.h"
#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
/* Macros to fill up division factors values */
#define z_pllm(v) LL_RCC_PLLM_DIV_ ## v
#define pllm(v) z_pllm(v)
#define z_pllp(v) LL_RCC_PLLP_DIV_ ## v
#define pllp(v) z_pllp(v)
/**
* @brief fill in pll configuration structure
*/
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
{
pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
pllinit->PLLP = pllp(CONFIG_CLOCK_STM32_PLL_P_DIVISOR);
}
#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
/**
* @brief Activate default clocks
*/
void config_enable_default_clocks(void)
{
/* Power Interface clock enabled by default */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
}
/**
* @brief Function kept for driver genericity
*/
void LL_RCC_MSI_Disable(void)
{
/* Do nothing */
}