f1f63dda17
This adds FPU sharing support with a lazy context switching algorithm. Every thread is allowed to use FPU/SIMD registers. In fact, the compiler may insert FPU reg accesses in anycontext to optimize even non-FP code unless the -mgeneral-regs-only compiler flag is used, but Zephyr currently doesn't support such a build. It is therefore possible to do FP access in IRS as well with this patch although IRQs are then disabled to prevent nested IRQs in such cases. Because the thread object grows in size, some tests have to be adjusted. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
181 lines
4.4 KiB
C
181 lines
4.4 KiB
C
/**
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* @file
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* @brief common definitions for the FPU sharing test application
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*/
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/*
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* Copyright (c) 2011-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _FLOATCONTEXT_H
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#define _FLOATCONTEXT_H
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/*
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* Each architecture must define the following structures (which may be empty):
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* 'struct fp_volatile_register_set'
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* 'struct fp_non_volatile_register_set'
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*
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* Each architecture must also define the following macros:
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* SIZEOF_FP_VOLATILE_REGISTER_SET
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* SIZEOF_FP_NON_VOLATILE_REGISTER_SET
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* Those macros are used as sizeof(<an empty structure>) is compiler specific;
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* that is, it may evaluate to a non-zero value.
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*
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* Each architecture shall also have custom implementations of:
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* _load_all_float_registers()
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* _load_then_store_all_float_registers()
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* _store_all_float_registers()
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*/
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#if defined(CONFIG_X86)
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#define FP_OPTION 0
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/*
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* In the future, the struct definitions may need to be refined based on the
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* specific IA-32 processor, but for now only the Pentium4 is supported:
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*
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* 8 x 80 bit floating point registers (ST[0] -> ST[7])
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* 8 x 128 bit XMM registers (XMM[0] -> XMM[7])
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*
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* All these registers are considered volatile across a function invocation.
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*/
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struct fp_register {
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unsigned char reg[10];
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};
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struct xmm_register {
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unsigned char reg[16];
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};
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struct fp_volatile_register_set {
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struct xmm_register xmm[8]; /* XMM[0] -> XMM[7] */
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struct fp_register st[8]; /* ST[0] -> ST[7] */
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};
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struct fp_non_volatile_register_set {
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/* No non-volatile floating point registers */
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};
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#define SIZEOF_FP_VOLATILE_REGISTER_SET sizeof(struct fp_volatile_register_set)
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#define SIZEOF_FP_NON_VOLATILE_REGISTER_SET 0
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_FP)
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#define FP_OPTION 0
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/*
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* Registers s0..s15 are volatile and do not
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* need to be preserved across function calls.
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*/
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struct fp_volatile_register_set {
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float s[16];
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};
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/*
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* Registers s16..s31 are non-volatile and
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* need to be preserved across function calls.
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*/
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struct fp_non_volatile_register_set {
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float s[16];
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};
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#define SIZEOF_FP_VOLATILE_REGISTER_SET \
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sizeof(struct fp_volatile_register_set)
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#define SIZEOF_FP_NON_VOLATILE_REGISTER_SET \
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sizeof(struct fp_non_volatile_register_set)
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#elif defined(CONFIG_ARM64)
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struct fp_volatile_register_set {
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__int128 regs[16]; /* q0..q15 */
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};
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struct fp_non_volatile_register_set {
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__int128 regs[16]; /* q16..q31 */
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};
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#define SIZEOF_FP_VOLATILE_REGISTER_SET \
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sizeof(struct fp_volatile_register_set)
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#define SIZEOF_FP_NON_VOLATILE_REGISTER_SET \
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sizeof(struct fp_non_volatile_register_set)
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#elif defined(CONFIG_ISA_ARCV2)
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struct fp_volatile_register_set {
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#ifdef CONFIG_FP_FPU_DA
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uint32_t dpfp2h;
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uint32_t dpfp2l;
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uint32_t dpfp1h;
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uint32_t dpfp1l;
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#endif
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};
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struct fp_non_volatile_register_set {
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/* No non-volatile floating point registers */
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};
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#define SIZEOF_FP_VOLATILE_REGISTER_SET sizeof(struct fp_volatile_register_set)
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#define SIZEOF_FP_NON_VOLATILE_REGISTER_SET 0
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#elif defined(CONFIG_RISCV)
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struct fp_volatile_register_set {
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#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
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uint64_t fp[32];
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#else
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uint32_t fp[32];
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#endif
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};
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struct fp_non_volatile_register_set {
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/* No non-volatile floating point registers */
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};
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#define SIZEOF_FP_VOLATILE_REGISTER_SET sizeof(struct fp_volatile_register_set)
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#define SIZEOF_FP_NON_VOLATILE_REGISTER_SET 0
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#elif defined(CONFIG_SPARC)
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struct fp_volatile_register_set {
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double d[16];
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};
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struct fp_non_volatile_register_set {
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};
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#define SIZEOF_FP_VOLATILE_REGISTER_SET sizeof(struct fp_volatile_register_set)
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#define SIZEOF_FP_NON_VOLATILE_REGISTER_SET 0
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#else
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#error "Architecture must provide the following definitions:\n"
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"\t'struct fp_volatile_registers'\n"
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"\t'struct fp_non_volatile_registers'\n"
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"\t'SIZEOF_FP_VOLATILE_REGISTER_SET'\n"
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"\t'SIZEOF_FP_NON_VOLATILE_REGISTER_SET'\n"
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#endif /* CONFIG_X86 */
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/* the set of ALL floating point registers */
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struct fp_register_set {
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struct fp_volatile_register_set fp_volatile;
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struct fp_non_volatile_register_set fp_non_volatile;
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};
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#define SIZEOF_FP_REGISTER_SET \
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(SIZEOF_FP_VOLATILE_REGISTER_SET + SIZEOF_FP_NON_VOLATILE_REGISTER_SET)
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/*
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* The following constants define the initial byte value used by the background
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* task, and the thread when loading up the floating point registers.
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*/
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#define MAIN_FLOAT_REG_CHECK_BYTE ((unsigned char)0xe5)
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#define FIBER_FLOAT_REG_CHECK_BYTE ((unsigned char)0xf9)
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#endif /* _FLOATCONTEXT_H */
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