7e0d006851
Support uart driver for qemu_rx environment base on the SCI0 HW on RX MCU Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
528 lines
16 KiB
C
528 lines
16 KiB
C
/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_rx_uart_sci
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#include <zephyr/drivers/uart.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <soc.h>
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#include <zephyr/irq.h>
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#include <zephyr/spinlock.h>
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#include "r_sci_rx_if.h"
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#if CONFIG_SOC_SERIES_RX130
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#include "r_sci_rx130_private.h"
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#else
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#error Unknown SOC, not (yet) supported.
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#endif
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(rx_uart_sci, CONFIG_UART_LOG_LEVEL);
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#define DEV_CFG(dev) ((const struct uart_rx_sci_config *const)(dev)->config)
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#define DEV_BASE(dev) (DEV_CFG(dev)->regs)
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#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
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static void uart_rx_sci_txi_isr(const struct device *dev);
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#endif
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/* SCI SCR register */
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#define R_SCI_SCR_TIE_Pos (SCI_BIT7)
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#define R_SCI_SCR_RIE_Pos (SCI_BIT6)
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#define R_SCI_SCR_TEIE_Pos (SCI_BIT2)
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/* SCI SSR register */
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#define R_SCI_SSR_TDRE_Pos (SCI_BIT7)
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#define R_SCI_SSR_RDRF_Pos (SCI_BIT6)
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#define R_SCI_SSR_ORER_Pos (SCI_BIT5)
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#define R_SCI_SSR_FER_Pos (SCI_BIT4)
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#define R_SCI_SSR_PER_Pos (SCI_BIT3)
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#define R_SCI_SSR_TEND_Pos (SCI_BIT2)
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struct uart_rx_sci_config {
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uint32_t regs;
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const struct pinctrl_dev_config *pcfg;
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};
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struct uart_rx_sci_data {
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const struct device *dev;
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uint8_t channel;
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sci_hdl_t hdl;
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struct uart_config uart_config;
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sci_cfg_t sci_config;
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#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
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uint8_t rxi_irq;
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uint8_t txi_irq;
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uint8_t tei_irq;
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uint8_t eri_irq;
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uart_irq_callback_user_data_t user_cb;
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void *user_cb_data;
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#endif
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};
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static int uart_rx_sci_poll_in(const struct device *dev, unsigned char *c)
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{
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volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev);
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if (IS_ENABLED(CONFIG_UART_ASYNC_API) && sci->SCR.BIT.RIE) {
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return -EBUSY;
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}
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if (sci->SSR.BIT.RDRF == 0U) {
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/* There are no characters available to read. */
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return -1;
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}
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*c = (unsigned char)sci->RDR;
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return 0;
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}
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static void uart_rx_sci_poll_out(const struct device *dev, unsigned char c)
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{
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volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev);
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while (sci->SSR.BIT.TEND == 0U) {
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}
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sci->TDR = c;
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}
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static int uart_rx_err_check(const struct device *dev)
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{
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volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev);
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const uint32_t status = sci->SSR.BYTE;
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int errors = 0;
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if ((status & BIT(R_SCI_SSR_ORER_Pos)) != 0) {
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errors |= UART_ERROR_OVERRUN;
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sci->SSR.BIT.ORER = 0;
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}
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if ((status & BIT(R_SCI_SSR_PER_Pos)) != 0) {
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errors |= UART_ERROR_PARITY;
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sci->SSR.BIT.PER = 0;
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}
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if ((status & BIT(R_SCI_SSR_FER_Pos)) != 0) {
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errors |= UART_ERROR_FRAMING;
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sci->SSR.BIT.FER = 0;
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}
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return errors;
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}
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static int uart_rx_sci_apply_config(const struct uart_config *config, sci_cfg_t *uart_config)
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{
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switch (config->data_bits) {
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case UART_CFG_DATA_BITS_5:
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return -ENOTSUP;
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case UART_CFG_DATA_BITS_6:
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return -ENOTSUP;
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case UART_CFG_DATA_BITS_7:
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uart_config->async.data_size = SCI_DATA_7BIT;
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break;
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case UART_CFG_DATA_BITS_8:
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uart_config->async.data_size = SCI_DATA_8BIT;
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break;
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case UART_CFG_DATA_BITS_9:
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return -ENOTSUP;
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default:
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return -EINVAL;
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}
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switch (config->parity) {
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case UART_CFG_PARITY_NONE:
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uart_config->async.parity_en = SCI_PARITY_OFF;
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uart_config->async.parity_type = SCI_EVEN_PARITY;
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break;
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case UART_CFG_PARITY_ODD:
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uart_config->async.parity_en = SCI_PARITY_ON;
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uart_config->async.parity_type = SCI_ODD_PARITY;
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break;
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case UART_CFG_PARITY_EVEN:
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uart_config->async.parity_en = SCI_PARITY_ON;
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uart_config->async.parity_type = SCI_EVEN_PARITY;
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break;
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case UART_CFG_PARITY_MARK:
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return -ENOTSUP;
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case UART_CFG_PARITY_SPACE:
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return -ENOTSUP;
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default:
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return -EINVAL;
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}
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switch (config->stop_bits) {
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case UART_CFG_STOP_BITS_0_5:
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return -ENOTSUP;
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case UART_CFG_STOP_BITS_1:
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uart_config->async.stop_bits = SCI_STOPBITS_1;
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break;
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case UART_CFG_STOP_BITS_1_5:
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return -ENOTSUP;
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case UART_CFG_STOP_BITS_2:
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uart_config->async.stop_bits = SCI_STOPBITS_2;
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break;
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case UART_CFG_PARITY_SPACE:
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return -ENOTSUP;
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default:
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return -EINVAL;
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}
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uart_config->async.baud_rate = config->baudrate;
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uart_config->async.clk_src = SCI_CLK_INT;
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uart_config->async.int_priority = 4;
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return 0;
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}
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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static int uart_rx_configure(const struct device *dev, const struct uart_config *cfg)
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{
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int err;
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sci_err_t sci_err;
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struct uart_rx_sci_data *data = dev->data;
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err = uart_rx_sci_apply_config(cfg, &data->sci_config);
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if (err) {
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return err;
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}
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sci_err = R_SCI_Close(data->hdl);
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if (sci_err) {
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return -EIO;
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}
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sci_err = R_SCI_Open(data->channel, SCI_MODE_ASYNC, &data->sci_config, NULL, &data->hdl);
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if (sci_err) {
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return -EIO;
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}
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memcpy(&data->uart_config, cfg, sizeof(struct uart_config));
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return 0;
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}
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static int uart_rx_config_get(const struct device *dev, struct uart_config *cfg)
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{
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struct uart_rx_sci_data *data = dev->data;
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memcpy(cfg, &data->uart_config, sizeof(*cfg));
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return 0;
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}
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#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int uart_rx_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
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{
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volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev);
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uint8_t num_tx = 0U;
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if (size > 0 && sci->SSR.BIT.TDRE) {
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/* Send a character (8bit , parity none) */
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sci->TDR = tx_data[num_tx++];
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}
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return num_tx;
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}
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static int uart_rx_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
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{
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volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev);
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uint8_t num_rx = 0U;
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if (size > 0 && sci->SSR.BIT.RDRF) {
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/* Receive a character (8bit , parity none) */
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rx_data[num_rx++] = sci->RDR;
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}
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return num_rx;
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}
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static void uart_rx_irq_tx_enable(const struct device *dev)
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{
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struct uart_rx_sci_data *data = dev->data;
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volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev);
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sci->SCR.BYTE |= (BIT(R_SCI_SCR_TIE_Pos) | BIT(R_SCI_SCR_TEIE_Pos));
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irq_enable(data->tei_irq);
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if (sci->SSR.BIT.TDRE) {
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/* the callback function is usually called from an interrupt,
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* preventing other interrupts to be triggered during execution
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* just to be sure, lock interrupts while the callback is
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* handled.
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*/
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uint32_t key = irq_lock();
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uart_rx_sci_txi_isr(dev);
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irq_unlock(key);
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}
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}
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static void uart_rx_irq_tx_disable(const struct device *dev)
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{
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struct uart_rx_sci_data *data = dev->data;
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volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev);
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sci->SCR.BYTE &= ~(BIT(R_SCI_SCR_TIE_Pos) | BIT(R_SCI_SCR_TEIE_Pos));
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irq_disable(data->tei_irq);
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}
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static int uart_rx_irq_tx_ready(const struct device *dev)
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{
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volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev);
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return (sci->SCR.BIT.TIE == 1U) &&
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(sci->SSR.BYTE & (BIT(R_SCI_SSR_TDRE_Pos) | BIT(R_SCI_SSR_TEND_Pos)));
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}
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static int uart_rx_irq_tx_complete(const struct device *dev)
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{
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volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev);
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return (sci->SCR.BIT.TEIE == 1U) && (sci->SSR.BYTE & BIT(R_SCI_SSR_TEND_Pos));
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}
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static void uart_rx_irq_rx_enable(const struct device *dev)
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{
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volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev);
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sci->SCR.BIT.RIE = 1U;
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}
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static void uart_rx_irq_rx_disable(const struct device *dev)
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{
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volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev);
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sci->SCR.BIT.RIE = 0U;
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}
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static int uart_rx_irq_rx_ready(const struct device *dev)
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{
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volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev);
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return (sci->SCR.BIT.RIE == 1U) && ((sci->SSR.BYTE & BIT(R_SCI_SSR_RDRF_Pos)));
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}
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static void uart_rx_irq_err_enable(const struct device *dev)
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{
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struct uart_rx_sci_data *data = dev->data;
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irq_enable(data->eri_irq);
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}
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static void uart_rx_irq_err_disable(const struct device *dev)
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{
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struct uart_rx_sci_data *data = dev->data;
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irq_disable(data->eri_irq);
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}
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static int uart_rx_irq_is_pending(const struct device *dev)
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{
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volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev);
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bool tx_pending = false;
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bool rx_pending = false;
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tx_pending = ((sci->SCR.BYTE & BIT(R_SCI_SCR_TIE_Pos)) &&
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(sci->SSR.BYTE & (BIT(R_SCI_SSR_TEND_Pos) | BIT(R_SCI_SSR_TDRE_Pos))));
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rx_pending = ((sci->SCR.BYTE & BIT(R_SCI_SCR_RIE_Pos)) &&
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((sci->SSR.BYTE & (BIT(R_SCI_SSR_RDRF_Pos) | BIT(R_SCI_SSR_PER_Pos) |
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BIT(R_SCI_SSR_FER_Pos) | BIT(R_SCI_SSR_ORER_Pos)))));
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return tx_pending || rx_pending;
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}
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static int uart_rx_irq_update(const struct device *dev)
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{
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return 1;
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}
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static void uart_rx_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
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void *cb_data)
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{
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struct uart_rx_sci_data *data = dev->data;
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data->user_cb = cb;
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data->user_cb_data = cb_data;
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static int uart_rx_init(const struct device *dev)
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{
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const struct uart_rx_sci_config *config = dev->config;
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struct uart_rx_sci_data *data = dev->data;
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int ret;
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sci_err_t sci_err;
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/* Configure dt provided device signals when available */
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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ret = uart_rx_sci_apply_config(&data->uart_config, &data->sci_config);
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if (ret) {
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return ret;
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}
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sci_err = R_SCI_Open(data->channel, SCI_MODE_ASYNC, &data->sci_config, NULL, &data->hdl);
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if (sci_err) {
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return -EIO;
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}
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/* Set the Asynchronous Start Bit Edge Detection Select to falling edge on the RXDn pin */
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sci_err = R_SCI_Control(data->hdl, SCI_CMD_START_BIT_EDGE, FIT_NO_PTR);
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if (sci_err) {
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return -EIO;
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}
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return 0;
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}
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static DEVICE_API(uart, uart_rx_driver_api) = {
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.poll_in = uart_rx_sci_poll_in,
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.poll_out = uart_rx_sci_poll_out,
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.err_check = uart_rx_err_check,
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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.configure = uart_rx_configure,
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.config_get = uart_rx_config_get,
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#endif
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = uart_rx_fifo_fill,
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.fifo_read = uart_rx_fifo_read,
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.irq_tx_enable = uart_rx_irq_tx_enable,
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.irq_tx_disable = uart_rx_irq_tx_disable,
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.irq_tx_ready = uart_rx_irq_tx_ready,
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.irq_rx_enable = uart_rx_irq_rx_enable,
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.irq_rx_disable = uart_rx_irq_rx_disable,
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.irq_tx_complete = uart_rx_irq_tx_complete,
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.irq_rx_ready = uart_rx_irq_rx_ready,
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.irq_err_enable = uart_rx_irq_err_enable,
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.irq_err_disable = uart_rx_irq_err_disable,
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.irq_is_pending = uart_rx_irq_is_pending,
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.irq_update = uart_rx_irq_update,
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.irq_callback_set = uart_rx_irq_callback_set,
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#endif
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};
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#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API
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static void uart_rx_sci_rxi_isr(const struct device *dev)
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{
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struct uart_rx_sci_data *data = dev->data;
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if (data->user_cb != NULL) {
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data->user_cb(dev, data->user_cb_data);
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}
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}
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static void uart_rx_sci_txi_isr(const struct device *dev)
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{
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struct uart_rx_sci_data *data = dev->data;
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if (data->user_cb != NULL) {
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data->user_cb(dev, data->user_cb_data);
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}
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}
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static void uart_rx_sci_tei_isr(const struct device *dev)
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{
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struct uart_rx_sci_data *data = dev->data;
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if (data->user_cb != NULL) {
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data->user_cb(dev, data->user_cb_data);
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}
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}
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static void uart_rx_sci_eri_isr(const struct device *dev)
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{
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struct uart_rx_sci_data *data = dev->data;
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if (data->user_cb != NULL) {
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data->user_cb(dev, data->user_cb_data);
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}
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}
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#endif
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#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API
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#define UART_RX_SCI_IRQ_INIT(index) \
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do { \
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IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq), \
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DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, priority), \
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uart_rx_sci_rxi_isr, DEVICE_DT_INST_GET(index), 0); \
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IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq), \
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DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, priority), \
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uart_rx_sci_txi_isr, DEVICE_DT_INST_GET(index), 0); \
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IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq), \
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DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, priority), \
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uart_rx_sci_tei_isr, DEVICE_DT_INST_GET(index), 0); \
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IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq), \
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DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, priority), \
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uart_rx_sci_eri_isr, DEVICE_DT_INST_GET(index), 0); \
|
|
irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq)); \
|
|
irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq)); \
|
|
irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq)); \
|
|
irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq)); \
|
|
} while (0)
|
|
#else
|
|
#define UART_RX_SCI_IRQ_INIT(index)
|
|
#endif
|
|
|
|
|
|
#define UART_RX_INIT(index) \
|
|
PINCTRL_DT_DEFINE(DT_INST_PARENT(index)); \
|
|
\
|
|
static const struct uart_rx_sci_config uart_rx_sci_config_##index = { \
|
|
.regs = DT_REG_ADDR(DT_INST_PARENT(index)), \
|
|
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(index)), \
|
|
}; \
|
|
\
|
|
static struct uart_rx_sci_data uart_rx_sci_data_##index = { \
|
|
.dev = DEVICE_DT_GET(DT_DRV_INST(index)), \
|
|
.channel = DT_PROP(DT_INST_PARENT(index), channel), \
|
|
.sci_config = {}, \
|
|
.uart_config = \
|
|
{ \
|
|
.baudrate = DT_INST_PROP(index, current_speed), \
|
|
.parity = UART_CFG_PARITY_NONE, \
|
|
.stop_bits = UART_CFG_STOP_BITS_1, \
|
|
.data_bits = UART_CFG_DATA_BITS_8, \
|
|
.flow_ctrl = UART_CFG_FLOW_CTRL_NONE, \
|
|
}, \
|
|
.rxi_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq), \
|
|
.txi_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq), \
|
|
.tei_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq), \
|
|
.eri_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq), \
|
|
}; \
|
|
\
|
|
static int uart_rx_init_##index(const struct device *dev) \
|
|
{ \
|
|
UART_RX_SCI_IRQ_INIT(index); \
|
|
int err = uart_rx_init(dev); \
|
|
if (err != 0) { \
|
|
return err; \
|
|
} \
|
|
return 0; \
|
|
}; \
|
|
\
|
|
DEVICE_DT_INST_DEFINE(index, uart_rx_init_##index, NULL, &uart_rx_sci_data_##index, \
|
|
&uart_rx_sci_config_##index, PRE_KERNEL_1, \
|
|
CONFIG_SERIAL_INIT_PRIORITY, &uart_rx_driver_api);
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(UART_RX_INIT)
|