e98ac235e6
Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
130 lines
4.0 KiB
Plaintext
130 lines
4.0 KiB
Plaintext
# Kconfig - interrupt controller configuration options
|
|
|
|
#
|
|
# Copyright (c) 2015 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
|
|
|
|
menu "Interrupt Controllers"
|
|
|
|
config LOAPIC
|
|
bool "LOAPIC"
|
|
default n
|
|
select IOAPIC
|
|
depends on X86
|
|
help
|
|
This option selects local APIC as the interrupt controller.
|
|
|
|
config LOAPIC_BASE_ADDRESS
|
|
hex "Local APIC Base Address"
|
|
default 0xFEE00000
|
|
depends on LOAPIC
|
|
help
|
|
This option specifies the base address of the Local APIC device.
|
|
|
|
config LOAPIC_SPURIOUS_VECTOR
|
|
bool "Handle LOAPIC spurious interrupts"
|
|
default n
|
|
depends on LOAPIC
|
|
help
|
|
A special situation may occur when a processor raises its task
|
|
priority to be greater than or equal to the level of the
|
|
interrupt for which the processor INTR signal is currently being
|
|
asserted. If at the time the INTA cycle is issued, the
|
|
interrupt that was to be dispensed has become masked (programmed
|
|
by software), the local APIC will deliver a spurious-interrupt
|
|
vector. Dispensing the spurious-interrupt vector does not affect
|
|
the ISR, so the handler for this vector should return without an EOI.
|
|
From x86 manual Volume 3 Section 10.9.
|
|
|
|
config LOAPIC_SPURIOUS_VECTOR_ID
|
|
int "LOAPIC spurious vector ID"
|
|
default -1
|
|
depends on LOAPIC_SPURIOUS_VECTOR
|
|
help
|
|
IDT vector to use for spurious LOAPIC interrupts. Note that some
|
|
arches (P6, Pentium) ignore the low 4 bits and fix them at 0xF.
|
|
If this value is left at -1 the last entry in the IDT will be used.
|
|
|
|
config IOAPIC
|
|
bool "IO-APIC"
|
|
default y
|
|
depends on LOAPIC
|
|
help
|
|
This option signifies that the target has an IO-APIC device. This
|
|
capability allows IO-APIC-dependent code to be included.
|
|
|
|
config IOAPIC_DEBUG
|
|
bool "IO-APIC Debugging"
|
|
default n
|
|
depends on IOAPIC
|
|
help
|
|
Enable debugging for IO-APIC driver.
|
|
|
|
config IOAPIC_BASE_ADDRESS
|
|
hex "IO-APIC Base Address"
|
|
default 0xFEC00000
|
|
depends on IOAPIC
|
|
help
|
|
This option specifies the base address of the IO-APIC device.
|
|
|
|
config IOAPIC_NUM_RTES
|
|
int "Number of Redirection Table Entries available"
|
|
default 24
|
|
depends on IOAPIC
|
|
help
|
|
This option indicates the maximum number of Redirection Table Entries
|
|
(RTEs) (one per IRQ available to the IO-APIC) made available to the
|
|
kernel, regardless of the number provided by the hardware itself. For
|
|
most efficient usage of memory, it should match the number of IRQ lines
|
|
needed by devices connected to the IO-APIC.
|
|
|
|
config MVIC
|
|
bool "Intel Quark D2000 Interrupt Controller (MVIC)"
|
|
default n
|
|
depends on X86
|
|
select X86_FIXED_IRQ_MAPPING
|
|
help
|
|
The MVIC (Intel Quark microcontroller D2000 Interrupt Controller) is
|
|
configured by default to support 32 external interrupt lines. Unlike the
|
|
traditional IA LAPIC/IOAPIC, the interrupt vectors in MVIC are fixed and
|
|
not programmable. In addition, the priorities of these interrupt
|
|
lines are also fixed.
|
|
|
|
config MVIC_TIMER_IRQ
|
|
int "IRQ line to use for timer interrupt"
|
|
range 0 15
|
|
default 0
|
|
depends on MVIC
|
|
help
|
|
Specify the IRQ line to use for the timer interrupt. This should be
|
|
an IRQ line unused by any hardware. If nested interrupts are enabled,
|
|
higher interrupt lines have priority.
|
|
|
|
config ARCV2_INTERRUPT_UNIT
|
|
bool "ARCv2 Interrupt Unit"
|
|
default y
|
|
depends on ARC
|
|
help
|
|
The ARCv2 interrupt unit has 16 allocated exceptions associated with
|
|
vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255.
|
|
The interrupt unit is optional in the ARCv2-based processors. When
|
|
building a processor, you can configure the processor to include an
|
|
interrupt unit. The ARCv2 interrupt unit is highly programmable.
|
|
|
|
source "drivers/interrupt_controller/Kconfig.stm32"
|
|
|
|
endmenu
|