d56f5f7b0e
To reduce the SEMC clock to a usable speed we had to divide down the output clock of System PLL2 PFD1. To do this I had to override the hardcoded defaults. This commit adds the flexibility to override them in your board files. Signed-off-by: Bas van Loon <bas@arch-embedded.com> |
||
|---|---|---|
| .. | ||
| adi/max32 | ||
| aesc | ||
| ambiq | ||
| amd/acp_6_0 | ||
| andestech | ||
| antmicro/myra | ||
| arm | ||
| aspeed | ||
| atmel | ||
| bflb | ||
| brcm | ||
| cdns | ||
| common | ||
| efinix/sapphire | ||
| ene | ||
| espressif | ||
| gaisler | ||
| gd/gd32 | ||
| infineon | ||
| intel | ||
| ite/ec | ||
| litex/litex_vexriscv | ||
| lowrisc/opentitan | ||
| mediatek/mt8xxx | ||
| microchip | ||
| native/inf_clock | ||
| neorv32 | ||
| nordic | ||
| nuvoton | ||
| nxp | ||
| oct/osd32mp15x | ||
| openhwgroup/cva6 | ||
| openisa/rv32m1 | ||
| qemu | ||
| quicklogic/eos_s3 | ||
| raspberrypi/rpi_pico | ||
| realtek/ec | ||
| renesas | ||
| renode | ||
| rockchip | ||
| sensry | ||
| sifive/sifive_freedom | ||
| silabs | ||
| snps | ||
| st/stm32 | ||
| starfive/jh71xx | ||
| telink/tlsr | ||
| ti | ||
| wch/ch32v | ||
| xen | ||
| xlnx | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Kconfig.v2 | ||