e6dd68ec89
Introduce `CONFIG_RISCV_GP_PURPOSE` choice to make sure that only one of `CONFIG_RISCV_GP` or `CONFIG_RISCV_CURRENT_VIA_GP` can be enabled, instead of relying of dependencies. To do that, introduce a new `CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING` that can be selected by SoC when it implemented global pointer (GP) initialization for relative addressing in its linker. `CONFIG_RISCV_GP` will be the default choice when `CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING=y` Signed-off-by: Yong Cong Sin <ycsin@meta.com> Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
25 lines
661 B
Plaintext
25 lines
661 B
Plaintext
# Copyright (c) 2023 Rivos Inc.
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
|
|
config SOC_OPENTITAN
|
|
select ATOMIC_OPERATIONS_C
|
|
select INCLUDE_RESET_VECTOR
|
|
select RISCV_ISA_RV32I
|
|
select RISCV_ISA_EXT_M
|
|
select RISCV_ISA_EXT_C
|
|
select RISCV_ISA_EXT_ZICSR
|
|
select RISCV_ISA_EXT_ZIFENCEI
|
|
select RISCV_ISA_EXT_ZBA
|
|
select RISCV_ISA_EXT_ZBB
|
|
select RISCV_ISA_EXT_ZBC
|
|
select RISCV_ISA_EXT_ZBS
|
|
select RISCV
|
|
select RISCV_PRIVILEGED
|
|
select RISCV_HAS_PLIC
|
|
select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
|
|
# OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode.
|
|
select RISCV_VECTORED_MODE
|
|
select GEN_IRQ_VECTOR_TABLE
|
|
imply XIP
|
|
select SOC_EARLY_INIT_HOOK
|