zephyr/arch
Yasushi SHOJI 51bc0a065c linker: Make alignment size for sw_isr_table configurable
sw_isr_table has two entries, an argument and an ISR function.  The
comment on struct _isr_table_entry in include/sw_isr_table.h says that
"This allows a table entry to be loaded [...] with one ldmia
instruction, on ARM [...]".  Some arch, e.g. SPARC, also has a double
word load instruction, "ldd", but the instruct must have address align
to double word or 8 bytes.

This commit makes the table alignment configurable.  It allows each
architecture to specify it, if needed.  The default value is 0 for no
alignment.

Signed-off-by: Yasushi SHOJI <y-shoji@ispace-inc.com>
2019-07-24 10:09:02 -07:00
..
arc arch: arc: build cache.c conditionally 2019-07-04 10:04:27 -04:00
arm arch: arm: cleanup workaround for QEMU Cortex-M3 2019-07-17 09:14:44 -07:00
common cleanup: include/: move misc/__assert.h to sys/__assert.h 2019-06-27 22:55:49 -04:00
nios2 cleanup: include/: move misc/util.h to sys/util.h 2019-06-27 22:55:49 -04:00
posix arch: POSIX: Fix race with unused threads 2019-07-19 11:37:34 +02:00
riscv32 cleanup: include/: move misc/util.h to sys/util.h 2019-06-27 22:55:49 -04:00
x86 x86: allow user mode to induce kernel oops 2019-07-16 18:09:49 -07:00
x86_64 cleanup: include/: move tracing.h to debug/tracing.h 2019-06-27 22:55:49 -04:00
xtensa arch: xtensa: Get CPU clock frequency from DTS 2019-07-24 15:10:02 +02:00
CMakeLists.txt license: cleanup: add SPDX Apache-2.0 license identifier 2019-04-07 08:45:22 -04:00
Kconfig linker: Make alignment size for sw_isr_table configurable 2019-07-24 10:09:02 -07:00