Andrew Boie 99368c7435 x86: optimize GDT space ... The CPU manual indicates that 8-byte alignment is sufficient, not sure why gdt_rom was aligned on a 16-byte boundary. The null descriptor in the GDT is never looked at by the CPU, save a few bytes by putting the 6-byte pseudo descriptor there. Change-Id: I73f26cdeb30a91f8258c88ef960a45812a11d959 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>		2016-09-20 20:47:15 +00:00
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arc	intel_quark: Group Quark SoCs under intel_quark/	2016-09-16 03:10:32 +00:00
arm	ARM: irq: Add _arch_irq_is_enabled external interrupt API	2016-09-20 19:45:31 +00:00
nios2	toolchain: Remove vestigial COFF assembler symbol mangling support	2016-08-30 19:01:11 +00:00
x86	x86: optimize GDT space	2016-09-20 20:47:15 +00:00
Kconfig	nanokernel: support GCC compiler atomic builtins	2016-07-18 23:20:52 +00:00
Makefile	arch/Makefile: simplify	2016-04-27 21:40:19 +00:00