Adrian Bonislawski 7918839ddd intel_adsp: ace30: Bring up ACE 3.0 (WCL) ... This commit adds definition of ACE 3.0 Wildcat Lake board Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>		2025-05-15 22:14:44 +02:00
..
adl	boards: intel: Updated TSC frequency values	2025-04-07 11:22:45 +02:00
adsp	intel_adsp: ace30: Bring up ACE 3.0 (WCL)	2025-05-15 22:14:44 +02:00
btl	boards: intel: btl: use zephyr board sphinx directives	2025-04-14 16:08:06 +02:00
common
ehl
ish	boards: intel: ish: Improve Simics support	2024-12-12 16:22:34 +01:00
niosv_g	boards: align vendor entry in board.yml files	2025-04-29 02:41:53 +02:00
niosv_m	boards: align vendor entry in board.yml files	2025-04-29 02:41:53 +02:00
rpl	boards: intel: rpl: Added revisions for RPL-s board	2025-05-09 01:40:09 +02:00
socfpga	boards: align vendor entry in board.yml files	2025-04-29 02:41:53 +02:00
socfpga_std/cyclonev_socdk	boards: align vendor entry in board.yml files	2025-04-29 02:41:53 +02:00
index.rst