06615c148d
This commit relaxes the precision requirements for idle event statistic test when RISC-V machine timer driver is used. This is needed for some platforms (e.g. hifive1), for which the cycle count is too low to pass the checks where a percent deviation of peak cycles count is allowed. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
13 lines
432 B
YAML
13 lines
432 B
YAML
tests:
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kernel.usage:
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tags: kernel
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# The following architectures are excluded as they have boards that
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# exhibit precision timing anomalies related to emulation.
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# posix, riscv32, sparc
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# The following architectures are exluded as the necessary
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# thread runtime statistic hooks do not yet exist.
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# mips
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arch_exclude: posix sparc mips
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# SMP is excluded as the test was only written for UP
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filter: not CONFIG_SMP
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