The nRF54 and nRF92 chips has data cache, which means the ICMsg and ICBMsg must be configured to follow required cache alignment of the shared memory. The `dcache-alignement` needs to be defined for that. Signed-off-by: Dominik Kilian <Dominik.Kilian@nordicsemi.no> |
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| .. | ||
| nrf54l15dk_nrf54l15_cpuflpr_icbmsg.overlay | ||
| nrf54l15dk_nrf54l15_cpuflpr.overlay | ||
| nrf5340bsim_nrf5340_cpunet.overlay | ||
| nrf5340dk_nrf5340_cpunet.overlay | ||
| stm32h747i_disco_stm32h747xx_m4.conf | ||
| stm32h747i_disco_stm32h747xx_m4.overlay | ||