74b53df064
In the Intel platforms most of HPSRAM is used by modules when are required. By default all these banks are powered off and are enabled by L2 MM driver only when needed. At the driver initialisation each unused page is unmaped and when whole HPSRAM bank is unused the power is switched off. Since mapping memory in MMU TLB and flushing it at system start is not needed and time consuming, this patch modifies the init sequence to avoid it. Additionally it adds MMU maping and unmaping for pages allocated from unused pool. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com> Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
93 lines
2.5 KiB
C
93 lines
2.5 KiB
C
/*
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* Copyright (c) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Header for agregating all defines for mm
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*
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*/
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#ifndef ZEPHYR_DRIVERS_SYSTEM_MM_DRV_INTEL_MTL_
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#define ZEPHYR_DRIVERS_SYSTEM_MM_DRV_INTEL_MTL_
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#define DT_DRV_COMPAT intel_adsp_mtl_tlb
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#include <zephyr/device.h>
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#include <zephyr/kernel.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/sys/__assert.h>
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#include <zephyr/sys/check.h>
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#include <zephyr/kernel/mm.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/mm/system_mm.h>
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#include <zephyr/sys/mem_blocks.h>
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#include <soc.h>
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#include <adsp_memory.h>
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#include <adsp_memory_regions.h>
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#include "mm_drv_common.h"
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#define TLB_BASE (mm_reg_t)DT_REG_ADDR(DT_NODELABEL(tlb))
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/*
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* Number of significant bits in the page index (defines the size of
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* the table)
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*/
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#define TLB_PADDR_SIZE DT_INST_PROP(0, paddr_size)
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#define TLB_EXEC_BIT BIT(DT_INST_PROP(0, exec_bit_idx))
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#define TLB_WRITE_BIT BIT(DT_INST_PROP(0, write_bit_idx))
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#define TLB_ENTRY_NUM (1 << TLB_PADDR_SIZE)
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#define TLB_PADDR_MASK ((1 << TLB_PADDR_SIZE) - 1)
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#define TLB_ENABLE_BIT BIT(TLB_PADDR_SIZE)
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/* This is used to translate from TLB entry back to physical address. */
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/* base address of TLB table */
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#define TLB_PHYS_BASE \
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(((L2_SRAM_BASE / CONFIG_MM_DRV_PAGE_SIZE) & ~TLB_PADDR_MASK) * CONFIG_MM_DRV_PAGE_SIZE)
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#define HPSRAM_SEGMENTS(hpsram_ebb_quantity) \
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((ROUND_DOWN((hpsram_ebb_quantity) + 31u, 32u) / 32u) - 1u)
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#define L2_SRAM_PAGES_NUM (L2_SRAM_SIZE / CONFIG_MM_DRV_PAGE_SIZE)
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#define MAX_EBB_BANKS_IN_SEGMENT 32
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#define SRAM_BANK_SIZE (128 * 1024)
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#define L2_SRAM_BANK_NUM (L2_SRAM_SIZE / SRAM_BANK_SIZE)
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#define IS_BIT_SET(value, idx) ((value) & (1 << (idx)))
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/**
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* Calculate TLB entry based on physical address.
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*
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* @param pa Page-aligned virutal address.
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* @return TLB entry value.
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*/
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static inline uint16_t pa_to_tlb_entry(uintptr_t pa)
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{
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return (((pa) / CONFIG_MM_DRV_PAGE_SIZE) & TLB_PADDR_MASK);
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}
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/**
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* Calculate physical address based on TLB entry.
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*
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* @param tlb_entry TLB entry value.
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* @return physcial address pointer.
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*/
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static inline uintptr_t tlb_entry_to_pa(uint16_t tlb_entry)
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{
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return ((((tlb_entry) & TLB_PADDR_MASK) *
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CONFIG_MM_DRV_PAGE_SIZE) + TLB_PHYS_BASE);
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}
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/**
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* Calculate virtual memory regions allocation based on
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* info from linker script.
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*
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* @param End address of staticaly allocated memory.
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* @return Error Code.
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*/
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int calculate_memory_regions(uintptr_t static_alloc_end_ptr);
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#endif /* ZEPHYR_DRIVERS_SYSTEM_MM_DRV_INTEL_MTL_ */
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