326d6059c6
On devices where the backup memory is part of the TAMP peripheral, the Backup Domain Protection prevents write to the backup registers. This fix disables the protection before writing registers and re-enables it afterwards. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
125 lines
3.9 KiB
C
125 lines
3.9 KiB
C
/*
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* Copyright (c) 2022 Google Inc
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_bbram
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#include <errno.h>
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#include <zephyr/drivers/bbram.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/util.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_rtc.h>
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LOG_MODULE_REGISTER(bbram, CONFIG_BBRAM_LOG_LEVEL);
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#define STM32_BKP_REG_BYTES 4
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#ifdef TAMP
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/* If a SoC has a TAMP peripherals, then the backup registers are defined there,
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* not in the RTC.
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*/
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#define STM32_BKP_REG_OFFSET (TAMP_BASE + offsetof(TAMP_TypeDef, BKP0R) - RTC_BASE)
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#else
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#define STM32_BKP_REG_OFFSET offsetof(RTC_TypeDef, BKP0R)
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#endif
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#define STM32_BKP_REG_INDEX(offset) ((offset) >> 2)
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#define STM32_BKP_REG_BYTE_INDEX(offset) ((offset)&0x3UL)
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#define STM32_BKP_REG(i) (((volatile uint32_t *)config->base_addr)[(i)])
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/** Device config */
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struct bbram_stm32_config {
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const struct device *parent;
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/* BBRAM base address */
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uintptr_t base_addr;
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/* BBRAM size in bytes. */
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int size;
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};
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static int bbram_stm32_read(const struct device *dev, size_t offset, size_t size, uint8_t *data)
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{
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const struct bbram_stm32_config *config = dev->config;
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uint32_t reg, begin, to_copy;
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if (size < 1 || offset + size > config->size) {
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return -EFAULT;
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}
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for (size_t read = 0; read < size; read += to_copy) {
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reg = STM32_BKP_REG(STM32_BKP_REG_INDEX(offset + read));
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begin = STM32_BKP_REG_BYTE_INDEX(offset + read);
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to_copy = MIN(STM32_BKP_REG_BYTES - begin, size - read);
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bytecpy(data + read, (uint8_t *)® + begin, to_copy);
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}
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return 0;
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}
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static int bbram_stm32_write(const struct device *dev, size_t offset, size_t size,
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const uint8_t *data)
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{
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const struct bbram_stm32_config *config = dev->config;
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uint32_t reg, begin, to_copy;
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if (size < 1 || offset + size > config->size) {
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return -EFAULT;
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}
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#if defined(PWR_CR_DBP) || defined(PWR_CR1_DBP) || defined(PWR_DBPCR_DBP) || defined(PWR_DBPR_DBP)
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LL_PWR_EnableBkUpAccess();
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#endif /* PWR_CR_DBP || PWR_CR1_DBP || PWR_DBPCR_DBP || PWR_DBPR_DBP */
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for (size_t written = 0; written < size; written += to_copy) {
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reg = STM32_BKP_REG(STM32_BKP_REG_INDEX(offset + written));
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begin = STM32_BKP_REG_BYTE_INDEX(offset + written);
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to_copy = MIN(STM32_BKP_REG_BYTES - begin, size - written);
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bytecpy((uint8_t *)® + begin, data + written, to_copy);
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STM32_BKP_REG(STM32_BKP_REG_INDEX(offset + written)) = reg;
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}
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#if defined(PWR_CR_DBP) || defined(PWR_CR1_DBP) || defined(PWR_DBPCR_DBP) || defined(PWR_DBPR_DBP)
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LL_PWR_DisableBkUpAccess();
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#endif /* PWR_CR_DBP || PWR_CR1_DBP || PWR_DBPCR_DBP || PWR_DBPR_DBP */
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return 0;
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}
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static int bbram_stm32_get_size(const struct device *dev, size_t *size)
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{
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const struct bbram_stm32_config *config = dev->config;
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*size = config->size;
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return 0;
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}
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static const struct bbram_driver_api bbram_stm32_driver_api = {
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.read = bbram_stm32_read,
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.write = bbram_stm32_write,
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.get_size = bbram_stm32_get_size,
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};
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static int bbram_stm32_init(const struct device *dev)
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{
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const struct bbram_stm32_config *config = dev->config;
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if (!device_is_ready(config->parent)) {
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LOG_ERR("Device %s is not ready", config->parent->name);
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return -ENODEV;
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}
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return 0;
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}
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#define BBRAM_INIT(inst) \
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static const struct bbram_stm32_config bbram_cfg_##inst = { \
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.parent = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
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.base_addr = DT_REG_ADDR(DT_INST_PARENT(inst)) + STM32_BKP_REG_OFFSET, \
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.size = DT_INST_PROP(inst, st_backup_regs) * STM32_BKP_REG_BYTES, \
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}; \
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DEVICE_DT_INST_DEFINE(inst, bbram_stm32_init, NULL, NULL, &bbram_cfg_##inst, PRE_KERNEL_1, \
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CONFIG_BBRAM_INIT_PRIORITY, &bbram_stm32_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(BBRAM_INIT);
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