ab2515ad26
IT8xxx2 uses a relatively slow SPI flash for ROM with a small 4k I-cache. As a result in large or busy applications, instruction fetch can be very costly due to I-cache misses. Since exception handling code is some of the hottest code in most applications, add an option (enabled by default) causing that code to execute out of RAM in order to improve performance. This is very similar to exception section placement on XIP niosii platforms (which has similar motivation), but can still be disabled by configuration. Signed-off-by: Peter Marheine <pmarheine@chromium.org> |
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| arc | ||
| arm | ||
| arm64 | ||
| mips | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| Kconfig | ||