Jordan Yates d8f186aa4a arch: common: semihost: add semihosting operations ... Add an API that utilizes the ARM semihosting mechanism to interact with the host system when a device is being emulated or run under a debugger. RISCV is implemented in terms of the ARM implementation, and therefore the ARM definitions cross enough architectures to be defined 'common'. Functionality is exposed as a separate API instead of syscall implementations (`_lseek`, `_open`, etc) due to various quirks with the ARM mechanisms that means function arguments are not standard. For more information see: https://developer.arm.com/documentation/dui0471/m/what-is-semihosting- Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au> impl		2022-04-21 13:04:52 +02:00
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CMakeLists.txt	arch: common: semihost: add semihosting operations	2022-04-21 13:04:52 +02:00
gen_isr_tables.py
isr_tables.c
Kconfig	arch: common: dedicated SEMIHOST symbol	2022-04-21 13:04:52 +02:00
nocache.ld	arm64: add nocache memory segment support	2021-10-20 08:56:40 -05:00
ramfunc.ld	cmake: Add support to add symbols to ramfunc section	2022-04-18 17:24:12 -07:00
rom_start_offset.ld
semihost.c	arch: common: semihost: add semihosting operations	2022-04-21 13:04:52 +02:00
sw_isr_common.c	all: Deprecate UTIL_LISTIFY and replace with LISTIFY	2022-03-08 11:03:30 +01:00
timing.c