Carlo Caione 34e0294652 arm: aarch32: Use proper sys functions for cache mainteinance ... This patchset is fixing two things: 1. The proper sys_* functions are used for cache mainteinance operations. 2. To check the status of the L1 cache the SCB registers are probed so the code is assuming a core architecture cache is present, thus make the code conditionally compiled on CONFIG_ARCH_CACHE. Signed-off-by: Carlo Caione <ccaione@baylibre.com>		2023-01-10 18:22:32 -05:00
..
arc	ARC: introduce reworked irq_offload implementation	2022-12-20 22:51:24 +01:00
arm	arm: aarch32: Use proper sys functions for cache mainteinance	2023-01-10 18:22:32 -05:00
arm64	arch/arm64: Implement ASID support in ARM64 MMU	2022-12-13 17:21:11 +09:00
common	include: add missing irq.h include	2022-10-11 18:05:17 +02:00
mips	include: types: remove ulong_t	2022-09-06 18:16:33 +02:00
nios2	arch: comply to coding guidelines MISRA C:2012 Rule 14.4	2022-07-20 09:28:38 -05:00
posix	arch: posix: Declare _posix_zephyr_main with int return type	2022-11-05 16:41:45 +09:00
riscv	riscv: Allow SOC to override arch_irq_{lock,unlock,unlocked}	2023-01-09 19:21:39 +01:00
sparc	SPARC: reduce z_thread_entry_wrapper	2022-08-03 12:05:49 +02:00
x86	arch/x86: Fix compilation error	2023-01-10 14:06:33 +00:00
xtensa	arch: xtensa: save FPU register in context switching	2022-12-27 13:23:17 +01:00
CMakeLists.txt
Kconfig	cache: Rework cache API	2022-12-01 13:40:56 -05:00