7a90ab448b
Change-Id: Ida4333b91ad322ff676cfbaa2ccaab0bdd38cd48 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
20 lines
565 B
C
20 lines
565 B
C
/* Intel x86 GCC specific test inline assembler functions and macros */
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/*
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* Copyright (c) 2015, Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _TEST_ASM_INLINE_GCC_H
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#define _TEST_ASM_INLINE_GCC_H
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#if !defined(__GNUC__) || !defined(CONFIG_X86)
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#error test_asm_inline_gcc.h goes only with x86 GCC
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#endif
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#define _trigger_isr_handler() __asm__ volatile("int %0" : : "i" (TEST_SOFT_INT) : "memory")
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#define _trigger_spur_handler() __asm__ volatile("int %0" : : "i" (TEST_SPUR_INT) : "memory")
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#endif /* _TEST_ASM_INLINE_GCC_H */
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