zephyr/tests/subsys/llext/testcase.yaml
Tom Burdick 73f1156c5e llext: Remove simple from llext test
The simple path and naming wasn't really right, there are no other tests
and the test suite has become quite automated and extensable to cover
most things we'd like to test with llext. Building, loading, and linking
of course.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2025-01-02 09:19:35 +01:00

126 lines
4.1 KiB
YAML

common:
tags: llext
platform_exclude:
# platforms with active issues
- numaker_pfm_m487 # See #63167
- s32z2xxdc2/s32z270/rtu0 # See commit 18a0660
- s32z2xxdc2/s32z270/rtu1 # See commit 18a0660
# platforms that are always skipped by the runtime filter
- qemu_cortex_m0
- qemu_xtensa/dc233c/mmu
integration_platforms:
- qemu_cortex_a9 # ARM Cortex-A9 (ARMv7-A ISA)
- qemu_cortex_r5 # ARM Cortex-R5 (ARMv7-R ISA)
- mps2/an385 # ARM Cortex-M3 (ARMv7-M ISA)
- mps2/an521/cpu0 # ARM Cortex-M33 (ARMv8-M ISA)
filter: not CONFIG_HARVARD
extra_configs:
- arch:arm64:CONFIG_LLEXT_HEAP_SIZE=128
extra_conf_files:
- prj.conf
tests:
# While there is in practice no value in compiling subsys/llext/*.c
# without actually running it to load some extension, let's keep it in
# good shape and ready to be used by additional architectures in the
# future.
llext.loader_build:
build_only: true
# Run the suite with all combinations of core Kconfig options for the LLEXT
# subsystem (storage type, ELF type, MPU/MMU etc). To focus on LLEXT issues,
# most tests include no_mem_protection.conf, which disables memory protection
# hardware completely.
llext.readonly:
arch_allow: # Xtensa needs writable storage
- arm
- riscv
- arc
filter: not CONFIG_MPU and not CONFIG_MMU
extra_conf_files: ['no_mem_protection.conf']
extra_configs:
- CONFIG_LLEXT_STORAGE_WRITABLE=n
llext.readonly_mpu:
min_ram: 128
arch_allow: arm # Xtensa needs writable storage, currently not supported on RISC-V
filter: CONFIG_ARCH_HAS_USERSPACE
extra_configs:
- CONFIG_USERSPACE=y
- CONFIG_LLEXT_STORAGE_WRITABLE=n
llext.readonly_mmu:
arch_allow:
- arm64
- arm
- riscv
filter: CONFIG_MMU or CONFIG_RISCV_PMP
integration_platforms:
- qemu_cortex_a53 # ARM Cortex-A53 (ARMv8-A ISA)
extra_configs:
- CONFIG_LLEXT_HEAP_SIZE=128 # qemu_cortex_a9 requires larger heap
- CONFIG_LLEXT_STORAGE_WRITABLE=n
llext.writable:
arch_allow:
- arm
- xtensa
- riscv
- arc
integration_platforms:
- qemu_xtensa/dc233c # Xtensa ISA
filter: not CONFIG_MPU and not CONFIG_MMU
extra_conf_files: ['no_mem_protection.conf']
extra_configs:
- CONFIG_LLEXT_STORAGE_WRITABLE=y
llext.writable_relocatable:
arch_allow:
- arm
- xtensa
- riscv
- arc
platform_exclude:
- qemu_arc/qemu_arc_hs5x # See #80949
- nsim/nsim_hs5x # See #80949
- nsim/nsim_hs5x/smp # See #80949
- nsim/nsim_hs5x/smp/12cores # See #80949
integration_platforms:
- qemu_xtensa/dc233c # Xtensa ISA
filter: not CONFIG_MPU and not CONFIG_MMU
extra_conf_files: ['no_mem_protection.conf']
extra_configs:
- CONFIG_LLEXT_STORAGE_WRITABLE=y
- CONFIG_LLEXT_TYPE_ELF_RELOCATABLE=y
# Test the Symbol Link Identifier (SLID) linking feature on writable
# storage to cover both ARM and Xtensa architectures on the same test.
llext.writable_slid_linking:
arch_allow:
- arm
- xtensa
- riscv
- arc
integration_platforms:
- qemu_xtensa/dc233c # Xtensa ISA
filter: not CONFIG_MPU and not CONFIG_MMU
extra_conf_files: ['no_mem_protection.conf']
extra_configs:
- CONFIG_LLEXT_STORAGE_WRITABLE=y
- CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID=y
llext.writable_relocatable_slid_linking:
arch_allow:
- arm
- xtensa
- riscv
- arc
platform_exclude:
- qemu_arc/qemu_arc_hs5x # See #80949
- nsim/nsim_hs5x # See #80949
- nsim/nsim_hs5x/smp # See #80949
- nsim/nsim_hs5x/smp/12cores # See #80949
integration_platforms:
- qemu_xtensa/dc233c # Xtensa ISA
filter: not CONFIG_MPU and not CONFIG_MMU
extra_conf_files: ['no_mem_protection.conf']
extra_configs:
- CONFIG_LLEXT_STORAGE_WRITABLE=y
- CONFIG_LLEXT_TYPE_ELF_RELOCATABLE=y
- CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID=y