Michael Hope ab3fb336c4 dts: add the ch32v003 dtsi ... This commit adds the dtsi and bindings for the WCH CH32V003 which is a 32-bit general-purpose RISC-V MCU. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>		2024-11-26 14:41:46 +00:00
..
altr,nios2f.yaml
andes,andescore-v5.yaml	dts/riscv/andes: add andestech,andescore-v5 compatible string	2024-01-31 10:41:49 +01:00
arm,cortex-a53.yaml
arm,cortex-a55.yaml
arm,cortex-a72.yaml
arm,cortex-a76.yaml
arm,cortex-m0.yaml
arm,cortex-m0+.yaml
arm,cortex-m1.yaml
arm,cortex-m3.yaml
arm,cortex-m4.yaml
arm,cortex-m4f.yaml
arm,cortex-m7.yaml
arm,cortex-m23.yaml
arm,cortex-m33.yaml
arm,cortex-m33f.yaml
arm,cortex-m55.yaml	dts: bindings: cpu: add definition for arm,cortex-m55	2024-06-27 20:06:06 -04:00
arm,cortex-m55f.yaml	dts: bindings: cpu: add definition for arm,cortex-m55	2024-06-27 20:06:06 -04:00
arm,cortex-m85.yaml	arch: arm: Add initial support for Cortex-M85 Core	2024-06-26 13:36:14 -04:00
arm,cortex-m85f.yaml	arch: arm: Add initial support for Cortex-M85 Core	2024-06-26 13:36:14 -04:00
arm,cortex-m.yaml
arm,cortex-r4.yaml
arm,cortex-r4f.yaml
arm,cortex-r5.yaml
arm,cortex-r5f.yaml
arm,cortex-r7.yaml
arm,cortex-r52.yaml
arm,cortex-r82.yaml
cdns,tensilica-xtensa-lx3.yaml
cdns,tensilica-xtensa-lx4.yaml
cdns,tensilica-xtensa-lx6.yaml
cdns,tensilica-xtensa-lx7.yaml
cpu.yaml
efinix,vexriscv-sapphire.yaml	dts/riscv/efinix: add the efinix,vexriscv-sapphire compatible string	2024-01-31 10:41:49 +01:00
espressif,riscv.yaml	soc: esp32c2: Add support to ESP32C2 and ESP8684	2024-08-16 14:08:22 -04:00
espressif,xtensa-lx6.yaml	soc: esp32xx: refactor clock and RTC subsystems	2024-05-27 01:37:18 -07:00
espressif,xtensa-lx7.yaml	soc: esp32xx: refactor clock and RTC subsystems	2024-05-27 01:37:18 -07:00
gaisler,leon3.yaml
intel,alder-lake.yaml
intel,apollo-lake.yaml
intel,elkhart-lake.yaml
intel,ish.yaml
intel,lakemont.yaml
intel,niosv.yaml
intel,raptor-lake.yaml
intel,x86.yaml
ite,riscv-ite.yaml
litex,vexriscv-standard.yaml	dts/riscv/litex: add litex,vexriscv-standard compatible string	2024-01-31 10:41:49 +01:00
lowrisc,ibex.yaml	dts/riscv/lowrisc: add lowrisc,ibex compatible string	2024-01-31 10:41:49 +01:00
neorv32-cpu.yaml
nordic,vpr.yaml	dts: Add and extend Nordic bindings needed for nRF54H20	2024-02-02 16:40:11 +01:00
nuclei,bumblebee.yaml
openisa,ri5cy.yaml	dts/riscv/openisa: add compatible strings for the RI5CY cores	2024-01-31 10:41:49 +01:00
openisa,zero-ri5cy.yaml	dts/riscv/openisa: add compatible strings for the RI5CY cores	2024-01-31 10:41:49 +01:00
qemu,nios2-zephyr.yaml
qemu,riscv-virt.yaml	dts: set the riscv,isa property for virt-based targets	2024-05-15 09:30:23 +02:00
riscv,cpus.yaml	dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/	2024-01-31 10:41:49 +01:00
sample_controller.yaml
sensry,ganymed-sy1xx.yaml	soc: sensry: Add support for SY120-GBM and SY120-GEN1	2024-09-16 20:19:31 +02:00
sifive-common.yaml	dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/	2024-01-31 10:41:49 +01:00
sifive,e24.yaml	dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/	2024-01-31 10:41:49 +01:00
sifive,e31.yaml	dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/	2024-01-31 10:41:49 +01:00
sifive,e51.yaml	dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/	2024-01-31 10:41:49 +01:00
sifive,s7.yaml	dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/	2024-01-31 10:41:49 +01:00
sifive,u54.yaml	dts/riscv/microchip: add missing cpu nodes compats in mpfs.dtsi	2024-01-31 10:41:49 +01:00
snps,arcem.yaml
telink,b91.yaml
wch,qingke-v2.yaml	dts: add the ch32v003 dtsi	2024-11-26 14:41:46 +00:00
zephyr,native-posix-cpu.yaml