5107320075
Add a shell command to dump the isr_tables. ```CONFIG_SYMTAB=n uart:~$ isr_table sw_isr_table _sw_isr_table[1035] 7: 0x800056e2(0) 11: 0x80005048(0x80008148) 22: 0x800054ee(0x80008170) ``` ```CONFIG_SYMTAB=y uart:~$ isr_table sw_isr_table _sw_isr_table[1035] 7: timer_isr(0) 11: plic_irq_handler(0x80008188) 22: uart_ns16550_isr(0x800081b0) ``` Signed-off-by: Yong Cong Sin <ycsin@meta.com> Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
40 lines
1.3 KiB
Plaintext
40 lines
1.3 KiB
Plaintext
# Common architecture configuration options
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# Copyright (c) 2022, CSIRO.
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# SPDX-License-Identifier: Apache-2.0
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config SEMIHOST
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bool "Semihosting support for ARM and RISC-V targets"
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depends on ARM || ARM64 || RISCV
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help
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Semihosting is a mechanism that enables code running on an ARM or
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RISC-V target to communicate and use the Input/Output facilities on
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a host computer that is running a debugger.
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Additional information can be found in:
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https://developer.arm.com/documentation/dui0471/m/what-is-semihosting-
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https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
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This option is compatible with hardware and with QEMU, through the
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(automatic) use of the -semihosting-config switch when invoking it.
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config LEGACY_MULTI_LEVEL_TABLE_GENERATION
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bool "Auto generates the multi-level interrupt LUT (deprecated)"
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default y
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select DEPRECATED
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depends on MULTI_LEVEL_INTERRUPTS
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depends on !PLIC
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depends on !NXP_IRQSTEER
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depends on !RV32M1_INTMUX
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depends on !CAVS_ICTL
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depends on !DW_ICTL_ACE
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depends on !DW_ICTL
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help
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A make-shift Kconfig to continue generating the multi-level interrupt LUT
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with the legacy way using DT macros.
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config ISR_TABLE_SHELL
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bool "Shell command to dump the ISR tables"
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depends on GEN_SW_ISR_TABLE
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depends on SHELL
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help
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This option enables a shell command to dump the ISR tables.
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