a5eea17dda
This is a naive implementation which does "eager" context switching for floating-point context, which, of course, introduces performance concerns. Other approaches have security concerns, SMP implications, and impact the x86 arch and Zephyr project as a whole. Discussion is needed, so punting with the straightforward solution for now. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
61 lines
1.6 KiB
C
61 lines
1.6 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_ARCH_X86_INCLUDE_KERNEL_ARCH_DATA_H_
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#define ZEPHYR_ARCH_X86_INCLUDE_KERNEL_ARCH_DATA_H_
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/*
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* Exception/interrupt vector definitions: vectors 20 to 31 are reserved
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* for Intel; vectors 32 to 255 are user defined interrupt vectors.
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*/
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#define IV_DIVIDE_ERROR 0
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#define IV_DEBUG 1
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#define IV_NON_MASKABLE_INTERRUPT 2
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#define IV_BREAKPOINT 3
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#define IV_OVERFLOW 4
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#define IV_BOUND_RANGE 5
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#define IV_INVALID_OPCODE 6
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#define IV_DEVICE_NOT_AVAILABLE 7
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#define IV_DOUBLE_FAULT 8
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#define IV_COPROC_SEGMENT_OVERRUN 9
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#define IV_INVALID_TSS 10
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#define IV_SEGMENT_NOT_PRESENT 11
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#define IV_STACK_FAULT 12
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#define IV_GENERAL_PROTECTION 13
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#define IV_PAGE_FAULT 14
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#define IV_RESERVED 15
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#define IV_X87_FPU_FP_ERROR 16
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#define IV_ALIGNMENT_CHECK 17
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#define IV_MACHINE_CHECK 18
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#define IV_SIMD_FP 19
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#define IV_IRQS 32 /* start of vectors available for IRQs */
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#define IV_NR_VECTORS 256 /* total number of vectors */
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/*
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* EFLAGS/RFLAGS definitions. (RFLAGS is just zero-extended EFLAGS.)
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*/
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#define EFLAGS_IF 0x00000200U /* interrupts enabled */
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#define EFLAGS_INITIAL (EFLAGS_IF)
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/*
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* Control register definitions.
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*/
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#define CR0_PG 0x80000000 /* enable paging */
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#define CR0_WP 0x00010000 /* honor W bit even when supervisor */
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#define CR4_PAE 0x00000020 /* enable PAE */
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#define CR4_OSFXSR 0x00000200 /* enable SSE (OS FXSAVE/RSTOR) */
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#ifdef CONFIG_X86_LONGMODE
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#include <intel64/kernel_arch_data.h>
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#else
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#include <ia32/kernel_arch_data.h>
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#endif
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#endif /* ZEPHYR_ARCH_X86_INCLUDE_KERNEL_ARCH_DATA_H_ */
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