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Tomasz Bursztyka 5e4e0298e9 arch/x86: Generalize cache manipulation functions 
We assume that all x86 CPUs do have clflush instructions.
And the cache line size is now provided through DTS.

So detecting clflush instruction as well as the cache line size is no
longer required at runtime and thus removed.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-02-15 09:43:30 -05:00
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apollo_lake arch/x86: Generalize cache manipulation functions 2021-02-15 09:43:30 -05:00
atom arch/x86: Generalize cache manipulation functions 2021-02-15 09:43:30 -05:00
elkhart_lake arch/x86: Generalize cache manipulation functions 2021-02-15 09:43:30 -05:00
ia32 arch/x86: Generalize cache manipulation functions 2021-02-15 09:43:30 -05:00