b4afd1aecf
Add initial implementation of the uart async api for stm32 mcus. This uses the dma controller in normal mode for reception. In addition, to detect reception of bytes we enable the idle line detection interrupt. Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com> Signed-off-by: Jun Li <jun.r.li@intel.com> Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
75 lines
1.6 KiB
C
75 lines
1.6 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Driver for UART port on STM32 family processor.
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*
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*/
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#ifndef ZEPHYR_DRIVERS_SERIAL_UART_STM32_H_
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#define ZEPHYR_DRIVERS_SERIAL_UART_STM32_H_
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#include <drivers/pinmux.h>
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/* device config */
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struct uart_stm32_config {
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struct uart_device_config uconf;
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/* clock subsystem driving this peripheral */
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struct stm32_pclken pclken;
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/* initial hardware flow control, 1 for RTS/CTS */
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bool hw_flow_control;
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/* initial parity, 0 for none, 1 for odd, 2 for even */
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int parity;
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const struct soc_gpio_pinctrl *pinctrl_list;
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size_t pinctrl_list_size;
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};
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#ifdef CONFIG_UART_ASYNC_API
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struct uart_dma_stream {
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const char *dma_name;
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uint32_t dma_channel;
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struct dma_config dma_cfg;
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uint8_t priority;
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bool src_addr_increment;
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bool dst_addr_increment;
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int fifo_threshold;
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struct dma_block_config blk_cfg;
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uint8_t *buffer;
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size_t buffer_length;
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size_t offset;
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volatile size_t counter;
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int32_t timeout;
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struct k_delayed_work timeout_work;
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bool enabled;
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};
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#endif
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/* driver data */
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struct uart_stm32_data {
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/* Baud rate */
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uint32_t baud_rate;
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/* clock device */
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const struct device *clock;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t user_cb;
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void *user_data;
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#endif
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#ifdef CONFIG_UART_ASYNC_API
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const struct device *uart_dev;
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const struct device *dev_dma_tx;
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const struct device *dev_dma_rx;
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uart_callback_t async_cb;
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void *async_user_data;
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struct uart_dma_stream dma_rx;
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struct uart_dma_stream dma_tx;
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uint8_t *rx_next_buffer;
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size_t rx_next_buffer_len;
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#endif
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};
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#endif /* ZEPHYR_DRIVERS_SERIAL_UART_STM32_H_ */
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