1f4b5ddd0f
With the upcoming riscv64 support, it is best to use "riscv" as the subdirectory name and common symbols as riscv32 and riscv64 support code is almost identical. Then later decide whether 32-bit or 64-bit compilation is wanted. Redirects for the web documentation are also included. Then zephyrbot complained about this: " New files added that are not covered in CODEOWNERS: dts/riscv/microsemi-miv.dtsi dts/riscv/riscv32-fe310.dtsi Please add one or more entries in the CODEOWNERS file to cover those files " So I assigned them to those who created them. Feel free to readjust as necessary. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
54 lines
1.2 KiB
C
54 lines
1.2 KiB
C
/* GCC specific test inline assembler functions and macros */
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/*
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* Copyright (c) 2015, Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _TEST_ASM_INLINE_GCC_H
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#define _TEST_ASM_INLINE_GCC_H
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#if !defined(__GNUC__)
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#error test_asm_inline_gcc.h goes only with GCC
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#endif
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#if defined(CONFIG_X86)
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static inline void timestamp_serialize(void)
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{
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__asm__ __volatile__ (/* serialize */
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"xorl %%eax,%%eax;\n\t"
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"cpuid;\n\t"
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:
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:
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: "%eax", "%ebx", "%ecx", "%edx");
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}
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#elif defined(CONFIG_X86_64)
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static inline void timestamp_serialize(void)
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{
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__asm__ volatile("xorq %%rax,%%rax; cpuid"
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::: "rax", "rdx", "rbx", "rcx");
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}
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#elif defined(CONFIG_CPU_CORTEX_M)
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#include <arch/arm/cortex_m/cmsis.h>
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static inline void timestamp_serialize(void)
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{
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/* isb is available in all Cortex-M */
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__ISB();
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}
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#elif defined(CONFIG_CPU_ARCV2)
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#define timestamp_serialize()
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#elif defined(CONFIG_ARCH_POSIX)
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#define timestamp_serialize()
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#elif defined(CONFIG_XTENSA)
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#define timestamp_serialize()
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#elif defined(CONFIG_NIOS2)
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#define timestamp_serialize()
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#elif defined(CONFIG_RISCV)
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#define timestamp_serialize()
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#else
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#error implementation of timestamp_serialize() not provided for your CPU target
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#endif
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#endif /* _TEST_ASM_INLINE_GCC_H */
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