zephyr/dts/bindings/interrupt-controller
Nathaniel Graff 45d5d5db48 boards: riscv: Convert HiFive1 to DTS
Adds DTS bindings for sifive,pwm0, sifive,uart0, sifive,spi0, and
riscv,plic0.

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-08-13 18:35:38 -05:00
..
arm,v6m-nvic.yaml dts: Fix warning related to arm,v{6,7,8}m-nvic yaml files 2018-07-05 15:24:31 -05:00
arm,v7m-nvic.yaml dts: Fix warning related to arm,v{6,7,8}m-nvic yaml files 2018-07-05 15:24:31 -05:00
arm,v8m-nvic.yaml dts: Fix warning related to arm,v{6,7,8}m-nvic yaml files 2018-07-05 15:24:31 -05:00
intel,cavs-intc.yaml DTS: interrupt controller: Define IRQ priorities for CAVS & DW ICTL 2018-06-11 17:27:58 -04:00
intel,ioapic.yaml dts: Adding priority cell to Intel's IOAPIC IRQ controllers descriptor 2018-05-18 20:18:50 +03:00
intel,mvic.yaml scripts: extract_includes_dts: Remove usage of cell_string yaml attribute 2018-05-10 10:38:23 -05:00
riscv,plic0.yaml boards: riscv: Convert HiFive1 to DTS 2018-08-13 18:35:38 -05:00
snps,arcv2-intc.yaml dts: arc: fixes the warning msgs during cmake 2018-07-19 09:20:38 -05:00
snps,designware-intc.yaml dts: intel_s1000: Enable generating IRQ priority. 2018-05-22 09:30:14 -04:00
xtensa,intc.yaml DTS: interrupt controller: Define IRQ priorities for CAVS & DW ICTL 2018-06-11 17:27:58 -04:00