e3f2fa4f89
This interrupt controller is a designware IP that combines several sources of interrupt into one line that is then routed to the parent controller. This implementation supports only the regular irqs with no support for priority filtering and vectored interrupts. Firqs are also not supported. Change-Id: I8bdf6f8df4632b6d7e8a3ba9a77116771d034a48 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
144 lines
3.5 KiB
C
144 lines
3.5 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* This implementation supports only the regular irqs
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* No support for priority filtering
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* No support for vectored interrupts
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* Firqs are also not supported
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* This implementation works only when sw_isr_table is enabled in zephyr
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*/
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#include <device.h>
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#include <board.h>
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#include <irq_nextlevel.h>
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#include "dw_ictl.h"
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static ALWAYS_INLINE void dw_ictl_dispatch_child_isrs(u32_t intr_status,
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u32_t isr_base_offset)
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{
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u32_t intr_bitpos, intr_offset;
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/* Dispatch lower level ISRs depending upon the bit set */
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while (intr_status) {
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intr_bitpos = find_lsb_set(intr_status) - 1;
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intr_status &= ~(1 << intr_bitpos);
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intr_offset = isr_base_offset + intr_bitpos;
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_sw_isr_table[intr_offset].isr(
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_sw_isr_table[intr_offset].arg);
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}
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}
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static int dw_ictl_initialize(struct device *port)
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{
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struct dw_ictl_runtime *dw = port->driver_data;
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volatile struct dw_ictl_registers * const regs =
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(struct dw_ictl_registers *)dw->base_addr;
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/* disable all interrupts */
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regs->irq_inten_l = 0;
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regs->irq_inten_h = 0;
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return 0;
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}
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static void dw_ictl_isr(void *arg)
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{
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struct device *port = (struct device *)arg;
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struct dw_ictl_runtime * const dw = port->driver_data;
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const struct dw_ictl_config *config = port->config->config_info;
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volatile struct dw_ictl_registers * const regs =
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(struct dw_ictl_registers *)dw->base_addr;
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dw_ictl_dispatch_child_isrs(regs->irq_maskstatus_l,
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config->isr_table_offset);
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if (config->numirqs > 32) {
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dw_ictl_dispatch_child_isrs(regs->irq_maskstatus_h,
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config->isr_table_offset + 32);
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}
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}
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static inline void dw_ictl_intr_enable(struct device *dev, unsigned int irq)
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{
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struct dw_ictl_runtime *context = dev->driver_data;
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volatile struct dw_ictl_registers * const regs =
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(struct dw_ictl_registers *)context->base_addr;
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if (irq < 32) {
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regs->irq_inten_l |= (1 << irq);
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} else {
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regs->irq_inten_h |= (1 << (irq - 32));
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}
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}
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static inline void dw_ictl_intr_disable(struct device *dev, unsigned int irq)
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{
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struct dw_ictl_runtime *context = dev->driver_data;
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volatile struct dw_ictl_registers * const regs =
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(struct dw_ictl_registers *)context->base_addr;
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if (irq < 32) {
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regs->irq_inten_l &= ~(1 << irq);
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} else {
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regs->irq_inten_h &= ~(1 << (irq - 32));
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}
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}
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static inline unsigned int dw_ictl_intr_get_state(struct device *dev)
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{
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struct dw_ictl_runtime *context = dev->driver_data;
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const struct dw_ictl_config *config = dev->config->config_info;
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volatile struct dw_ictl_registers * const regs =
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(struct dw_ictl_registers *)context->base_addr;
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if (regs->irq_inten_l) {
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return 1;
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}
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if (config->numirqs > 32) {
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if (regs->irq_inten_h) {
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return 1;
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}
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}
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return 0;
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}
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static void dw_ictl_config_irq(struct device *port);
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static const struct dw_ictl_config dw_config = {
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.irq_num = DW_ICTL_IRQ,
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.numirqs = DW_ICTL_NUM_IRQS,
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.isr_table_offset = CONFIG_DW_ISR_TBL_OFFSET,
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.config_func = dw_ictl_config_irq,
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};
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static struct dw_ictl_runtime dw_runtime = {
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.base_addr = DW_ICTL_BASE_ADDR,
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};
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static const struct irq_next_level_api dw_ictl_apis = {
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.intr_enable = dw_ictl_intr_enable,
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.intr_disable = dw_ictl_intr_disable,
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.intr_get_state = dw_ictl_intr_get_state,
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};
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DEVICE_AND_API_INIT(dw_ictl, CONFIG_DW_ICTL_NAME, dw_ictl_initialize,
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&dw_runtime, &dw_config,
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POST_KERNEL, CONFIG_DW_ICTL_INIT_PRIORITY, &dw_ictl_apis);
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static void dw_ictl_config_irq(struct device *port)
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{
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IRQ_CONNECT(DW_ICTL_IRQ, CONFIG_DW_ICTL_IRQ_PRI, dw_ictl_isr,
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DEVICE_GET(dw_ictl), DW_ICTL_IRQ_FLAGS);
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}
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