6f3036091a
Legacy xtensa had a rather complicated implementation of en/disabling interrupts, owing to the "software priority" feature (which plays games with INTENABLE and INTLEVEL to allow for interrupts to interrupt each other outside their normal priorities). But that's not a Zephyr feature, it's enabled by a XT_USE_SWPRI value that comes from platform headers and isn't enabled on any of our boards. Dead code, basically. Replace with the obvious implementation when asm2 is in use. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
69 lines
1.3 KiB
C
69 lines
1.3 KiB
C
/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __XTENSA_API_H__
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#define __XTENSA_API_H__
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#include <xtensa/hal.h>
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#include "xtensa_rtos.h"
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#include "xtensa_context.h"
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/*
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* Call this function to enable the specified interrupts.
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*
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* mask - Bit mask of interrupts to be enabled.
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*/
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#if CONFIG_XTENSA_ASM2
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static inline void _xt_ints_on(unsigned int mask)
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{
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int val;
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__asm__ volatile("rsr.intenable %0" : "=r"(val));
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val |= mask;
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__asm__ volatile("wsr.intenable %0; rsync" : : "r"(val));
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}
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#else
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extern void _xt_ints_on(unsigned int mask);
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#endif
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/*
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* Call this function to disable the specified interrupts.
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*
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* mask - Bit mask of interrupts to be disabled.
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*/
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#if CONFIG_XTENSA_ASM2
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static inline void _xt_ints_off(unsigned int mask)
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{
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int val;
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__asm__ volatile("rsr.intenable %0" : "=r"(val));
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val &= ~mask;
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__asm__ volatile("wsr.intenable %0; rsync" : : "r"(val));
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}
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#else
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extern void _xt_ints_off(unsigned int mask);
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#endif
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/*
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* Call this function to set the specified (s/w) interrupt.
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*/
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static inline void _xt_set_intset(unsigned int arg)
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{
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xthal_set_intset(arg);
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}
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/* Call this function to clear the specified (s/w or edge-triggered)
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* interrupt.
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*/
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static inline void _xt_set_intclear(unsigned int arg)
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{
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xthal_set_intclear(arg);
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}
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#endif /* __XTENSA_API_H__ */
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