Martin Åberg feae3249b2 sparc: add support for thread local storage ... Adds the necessary bits to initialize TLS in the stack area and sets up CPU registers during context switch. Register g7 is used to point to the thread data. Thread data is accessed with negative offsets from g7. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>		2020-11-13 14:53:55 -08:00
..
arc	arc: enable thread local storage	2020-11-11 13:25:29 +01:00
arm	aarch64: mmu: Enable support for unprivileged EL0	2020-11-04 13:58:19 -08:00
common	ARCH: COMMON: split sys_io.h for MMIO & memory bits functions	2020-09-01 13:36:48 +02:00
nios2	arch: Apply dynamic IRQ API change	2020-09-02 13:48:13 +02:00
posix	Revert "posix: linker: Wrap rodata and rwdata in sections."	2020-09-02 14:46:01 -04:00
riscv	arch: riscv: linker: add support for userspace	2020-11-09 15:37:11 -05:00
sparc	sparc: add support for thread local storage	2020-11-13 14:53:55 -08:00
x86	x86: add support for common page tables	2020-11-05 09:33:40 -05:00
xtensa	xtensa: remove errno_var from strcut _thread_arch	2020-10-24 10:52:00 -07:00
arch_inlines.h	headers: Refactor kernel and arch headers.	2019-11-06 16:07:32 -08:00
cpu.h	arch: Add SPARC processor architecture	2020-11-13 14:53:55 -08:00
syscall.h	arch: riscv: add memory protection support	2020-11-09 15:37:11 -05:00