465e04cae7
This patch fixes calculations for the top of the interrupt and main stacks. Due to power of two alignment requirements for certain MPUs, the guard size must be taken into account due to the guard being counted against the initial stack size. Signed-off-by: Andy Gross <andy.gross@linaro.org>
61 lines
1.1 KiB
C
61 lines
1.1 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Stack helpers for Cortex-M CPUs
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*
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* Stack helper functions.
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*/
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#ifndef _ARM_CORTEXM_STACK__H_
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#define _ARM_CORTEXM_STACK__H_
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#include <kernel_structs.h>
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#include <asm_inline.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef _ASMLANGUAGE
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/* nothing */
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#else
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extern K_THREAD_STACK_DEFINE(_interrupt_stack, CONFIG_ISR_STACK_SIZE);
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/**
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*
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* @brief Setup interrupt stack
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*
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* On Cortex-M, the interrupt stack is registered in the MSP (main stack
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* pointer) register, and switched to automatically when taking an exception.
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void _InterruptStackSetup(void)
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{
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#ifdef CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
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u32_t msp = (u32_t)(K_THREAD_STACK_BUFFER(_interrupt_stack) +
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CONFIG_ISR_STACK_SIZE - MPU_GUARD_ALIGN_AND_SIZE);
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#else
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u32_t msp = (u32_t)(K_THREAD_STACK_BUFFER(_interrupt_stack) +
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CONFIG_ISR_STACK_SIZE);
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#endif
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_MspSet(msp);
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}
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ARM_CORTEXM_STACK__H_ */
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