725de70d86
Created structures and unions needed to enable the software to access these tables. Also updated the helper macros to ease the usage of the MMU page tables. JIRA: ZEP-2511 Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
418 lines
13 KiB
C
418 lines
13 KiB
C
/*
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* Copyright (c) 2010-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Private kernel definitions (IA-32)
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*
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* This file contains private kernel structures definitions and various
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* other definitions for the Intel Architecture 32 bit (IA-32) processor
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* architecture.
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* The header include/kernel.h contains the public kernel interface
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* definitions, with include/arch/x86/arch.h supplying the
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* IA-32 specific portions of the public kernel interface.
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*
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* This file is also included by assembly language files which must #define
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* _ASMLANGUAGE before including this header file. Note that kernel
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* assembly source files obtains structure offset values via "absolute symbols"
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* in the offsets.o module.
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*/
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/* this file is only meant to be included by kernel_structs.h */
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#ifndef _kernel_arch_data__h_
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#define _kernel_arch_data__h_
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <asm_inline.h>
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#include <exception.h>
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#include <kernel_arch_thread.h>
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#ifndef _ASMLANGUAGE
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#include <kernel.h>
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#include <nano_internal.h>
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#include <zephyr/types.h>
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#include <misc/dlist.h>
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#endif
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/* increase to 16 bytes (or more?) to support SSE/SSE2 instructions? */
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#define STACK_ALIGN_SIZE 4
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/* x86 Bitmask definitions for struct k_thread.thread_state */
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/* executing context is interrupt handler */
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#define _INT_ACTIVE (1 << 7)
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/* executing context is exception handler */
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#define _EXC_ACTIVE (1 << 6)
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#define _INT_OR_EXC_MASK (_INT_ACTIVE | _EXC_ACTIVE)
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/* end - states */
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#if defined(CONFIG_FP_SHARING) && defined(CONFIG_SSE)
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#define _FP_USER_MASK (K_FP_REGS | K_SSE_REGS)
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#elif defined(CONFIG_FP_SHARING)
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#define _FP_USER_MASK (K_FP_REGS)
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#endif
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/*
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* Exception/interrupt vector definitions: vectors 20 to 31 are reserved for
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* Intel; vectors 32 to 255 are user defined interrupt vectors.
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*/
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#define IV_DIVIDE_ERROR 0
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#define IV_DEBUG 1
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#define IV_NON_MASKABLE_INTERRUPT 2
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#define IV_BREAKPOINT 3
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#define IV_OVERFLOW 4
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#define IV_BOUND_RANGE 5
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#define IV_INVALID_OPCODE 6
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#define IV_DEVICE_NOT_AVAILABLE 7
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#define IV_DOUBLE_FAULT 8
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#define IV_COPROC_SEGMENT_OVERRUN 9
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#define IV_INVALID_TSS 10
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#define IV_SEGMENT_NOT_PRESENT 11
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#define IV_STACK_FAULT 12
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#define IV_GENERAL_PROTECTION 13
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#define IV_PAGE_FAULT 14
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#define IV_RESERVED 15
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#define IV_X87_FPU_FP_ERROR 16
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#define IV_ALIGNMENT_CHECK 17
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#define IV_MACHINE_CHECK 18
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#define IV_SIMD_FP 19
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#define IV_INTEL_RESERVED_END 31
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/*
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* Model specific register (MSR) definitions. Use the _MsrRead() and
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* _MsrWrite() primitives to read/write the MSRs. Only the so-called
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* "Architectural MSRs" are listed, i.e. the subset of MSRs and associated
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* bit fields which will not change on future processor generations.
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*/
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#define IA32_P5_MC_ADDR_MSR 0x0000
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#define IA32_P5_MC_TYPE_MSR 0x0001
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#define IA32_MONITOR_FILTER_SIZE_MSR 0x0006
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#define IA32_TIME_STAMP_COUNTER_MSR 0x0010
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#define IA32_IA32_SOC_ID_MSR 0x0017
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#define IA32_APIC_BASE_MSR 0x001b
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#define IA32_FEATURE_CONTROL_MSR 0x003a
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#define IA32_BIOS_SIGN_MSR 0x008b
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#define IA32_SMM_MONITOR_CTL_MSR 0x009b
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#define IA32_PMC0_MSR 0x00c1
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#define IA32_PMC1_MSR 0x00c2
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#define IA32_PMC2_MSR 0x00c3
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#define IA32_PMC3_MSR 0x00c4
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#define IA32_MPERF_MSR 0x00e7
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#define IA32_APERF_MSR 0x00e8
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#define IA32_MTRRCAP_MSR 0x00fe
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#define IA32_SYSENTER_CS_MSR 0x0174
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#define IA32_SYSENTER_ESP_MSR 0x0175
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#define IA32_SYSENTER_EIP_MSR 0x0176
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#define IA32_MCG_CAP_MSR 0x0179
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#define IA32_MCG_STATUS_MSR 0x017a
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#define IA32_MCG_CTL_MSR 0x017b
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#define IA32_PERFEVTSEL0_MSR 0x0186
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#define IA32_PERFEVTSEL1_MSR 0x0187
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#define IA32_PERFEVTSEL2_MSR 0x0188
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#define IA32_PERFEVTSEL3_MSR 0x0188
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#define IA32_PERF_STATUS_MSR 0x0198
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#define IA32_PERF_CTL_MSR 0x0199
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#define IA32_CLOCK_MODULATION_MSR 0x019a
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#define IA32_THERM_INTERRUPT_MSR 0x019b
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#define IA32_THERM_STATUS_MSR 0x019c
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#define IA32_MISC_ENABLE_MSR 0x01a0
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#define IA32_ENERGY_PERF_BIAS_MSR 0x01b0
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#define IA32_DEBUGCTL_MSR 0x01d9
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#define IA32_SMRR_PHYSBASE_MSR 0x01f2
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#define IA32_SMRR_PHYSMASK_MSR 0x01f3
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#define IA32_SOC_DCA_CAP_MSR 0x01f8
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#define IA32_CPU_DCA_CAP_MSR 0x01f9
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#define IA32_DCA_0_CAP_MSR 0x01fa
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#define IA32_MTRR_PHYSBASE0_MSR 0x0200
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#define IA32_MTRR_PHYSMASK0_MSR 0x0201
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#define IA32_MTRR_PHYSBASE1_MSR 0x0202
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#define IA32_MTRR_PHYSMASK1_MSR 0x0203
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#define IA32_MTRR_PHYSBASE2_MSR 0x0204
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#define IA32_MTRR_PHYSMASK2_MSR 0x0205
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#define IA32_MTRR_PHYSBASE3_MSR 0x0206
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#define IA32_MTRR_PHYSMASK3_MSR 0x0207
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#define IA32_MTRR_PHYSBASE4_MSR 0x0208
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#define IA32_MTRR_PHYSMASK4_MSR 0x0209
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#define IA32_MTRR_PHYSBASE5_MSR 0x020a
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#define IA32_MTRR_PHYSMASK5_MSR 0x020b
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#define IA32_MTRR_PHYSBASE6_MSR 0x020c
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#define IA32_MTRR_PHYSMASK6_MSR 0x020d
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#define IA32_MTRR_PHYSBASE7_MSR 0x020e
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#define IA32_MTRR_PHYSMASK7_MSR 0x020f
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#define IA32_MTRR_FIX64K_00000_MSR 0x0250
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#define IA32_MTRR_FIX16K_80000_MSR 0x0258
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#define IA32_MTRR_FIX16K_A0000_MSR 0x0259
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#define IA32_MTRR_FIX4K_C0000_MSR 0x0268
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#define IA32_MTRR_FIX4K_C8000_MSR 0x0269
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#define IA32_MTRR_FIX4K_D0000_MSR 0x026a
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#define IA32_MTRR_FIX4K_D8000_MSR 0x026b
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#define IA32_MTRR_FIX4K_E0000_MSR 0x026c
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#define IA32_MTRR_FIX4K_E8000_MSR 0x026d
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#define IA32_MTRR_FIX4K_F0000_MSR 0x026e
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#define IA32_MTRR_FIX4K_F8000_MSR 0x026f
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#define IA32_PAT_MSR 0x0277
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#define IA32_MC0_CTL2_MSR 0x0280
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#define IA32_MC1_CTL2_MSR 0x0281
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#define IA32_MC2_CTL2_MSR 0x0282
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#define IA32_MC3_CTL2_MSR 0x0283
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#define IA32_MC4_CTL2_MSR 0x0284
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#define IA32_MC5_CTL2_MSR 0x0285
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#define IA32_MC6_CTL2_MSR 0x0286
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#define IA32_MC7_CTL2_MSR 0x0287
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#define IA32_MC8_CTL2_MSR 0x0288
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#define IA32_MC9_CTL2_MSR 0x0289
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#define IA32_MC10_CTL2_MSR 0x028a
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#define IA32_MC11_CTL2_MSR 0x028b
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#define IA32_MC12_CTL2_MSR 0x028c
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#define IA32_MC13_CTL2_MSR 0x028d
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#define IA32_MC14_CTL2_MSR 0x028e
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#define IA32_MC15_CTL2_MSR 0x028f
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#define IA32_MC16_CTL2_MSR 0x0290
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#define IA32_MC17_CTL2_MSR 0x0291
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#define IA32_MC18_CTL2_MSR 0x0292
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#define IA32_MC19_CTL2_MSR 0x0293
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#define IA32_MC20_CTL2_MSR 0x0294
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#define IA32_MC21_CTL2_MSR 0x0295
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#define IA32_MTRR_DEF_TYPE_MSR 0x02ff
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#define IA32_FIXED_CTR0_MSR 0x0309
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#define IA32_FIXED_CTR1_MSR 0x030a
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#define IA32_FIXED_CTR2_MSR 0x030b
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#define IA32_PERF_CAPABILITIES_MSR 0x0345
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#define IA32_FIXED_CTR_CTL_MSR 0x038d
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#define IA32_PERF_GLOBAL_STATUS_MSR 0x038e
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#define IA32_PERF_GLOBAL_CTRL_MSR 0x038f
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#define IA32_PERF_GLOBAL_OVF_CTRL_MSR 0x0390
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#define IA32_PEBS_ENABLE_MSR 0x03f1
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#define IA32_MC0_CTL_MSR 0x0400
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#define IA32_MC0_STATUS 0x0401
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#define IA32_MC0_ADDR_MSR 0x0402
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#define IA32_MC0_MISC_MSR 0x0403
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#define IA32_MC1_CTL_MSR 0x0404
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#define IA32_MC1_STATUS_MSR 0x0405
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#define IA32_MC1_ADDR_MSR 0x0406
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#define IA32_MC1_MISC_MSR 0x0407
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#define IA32_MC2_CTL_MSR 0x0408
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#define IA32_MC2_STATUS_MSR 0x0409
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#define IA32_MC2_ADDR_MSR 0x040a
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#define IA32_MC2_MISC_MSR 0x040b
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#define IA32_MC3_CTL_MSR 0x040c
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#define IA32_MC3_STATUS_MSR 0x040d
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#define IA32_MC3_ADDR_MSR 0x040e
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#define IA32_MC3_MISC_MSR 0x040f
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#define IA32_MC4_CTL_MSR 0x0410
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#define IA32_MC4_STATUS_MSR 0x0411
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#define IA32_MC4_ADDR_MSR 0x0412
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#define IA32_MC4_MISC_MSR 0x0413
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#define IA32_MC5_CTL_MSR 0x0414
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#define IA32_MC5_STATUS_MSR 0x0415
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#define IA32_MC5_ADDR_MSR 0x0416
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#define IA32_MC5_MISC_MSR 0x0417
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#define IA32_MC6_CTL_MSR 0x0418
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#define IA32_MC6_STATUS_MSR 0x0419
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#define IA32_MC6_ADDR_MSR 0x041a
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#define IA32_MC6_MISC_MSR 0x041b
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#define IA32_MC7_CTL_MSR 0x041c
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#define IA32_MC7_STATUS_MSR 0x041d
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#define IA32_MC7_ADDR_MSR 0x041e
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#define IA32_MC7_MISC_MSR 0x041f
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#define IA32_MC8_CTL_MSR 0x0420
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#define IA32_MC8_STATUS_MSR 0x0421
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#define IA32_MC8_ADDR_MSR 0x0422
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#define IA32_MC8_MISC_MSR 0x0423
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#define IA32_MC9_CTL_MSR 0x0424
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#define IA32_MC9_STATUS_MSR 0x0425
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#define IA32_MC9_ADDR_MSR 0x0426
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#define IA32_MC9_MISC_MSR 0x0427
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#define IA32_MC9_CTL_MSR 0x0424
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#define IA32_MC9_STATUS_MSR 0x0425
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#define IA32_MC9_ADDR_MSR 0x0426
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#define IA32_MC9_MISC_MSR 0x0427
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#define IA32_MC9_CTL_MSR 0x0424
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#define IA32_MC9_STATUS_MSR 0x0425
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#define IA32_MC9_ADDR_MSR 0x0426
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#define IA32_MC9_MISC_MSR 0x0427
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#define IA32_MC9_CTL_MSR 0x0424
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#define IA32_MC9_STATUS_MSR 0x0425
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#define IA32_MC9_ADDR_MSR 0x0426
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#define IA32_MC9_MISC_MSR 0x0427
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#define IA32_MC10_CTL_MSR 0x0428
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#define IA32_MC10_STATUS_MSR 0x0429
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#define IA32_MC10_ADDR_MSR 0x042a
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#define IA32_MC10_MISC_MSR 0x042b
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#define IA32_MC11_CTL_MSR 0x042c
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#define IA32_MC11_STATUS_MSR 0x042d
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#define IA32_MC11_ADDR_MSR 0x042e
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#define IA32_MC11_MISC_MSR 0x042f
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#define IA32_MC12_CTL_MSR 0x0430
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#define IA32_MC12_STATUS_MSR 0x0431
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#define IA32_MC12_ADDR_MSR 0x0432
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#define IA32_MC12_MISC_MSR 0x0433
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#define IA32_MC13_CTL_MSR 0x0434
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#define IA32_MC13_STATUS_MSR 0x0435
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#define IA32_MC13_ADDR_MSR 0x0436
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#define IA32_MC13_MISC_MSR 0x0437
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#define IA32_MC14_CTL_MSR 0x0438
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#define IA32_MC14_STATUS_MSR 0x0439
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#define IA32_MC14_ADDR_MSR 0x043a
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#define IA32_MC14_MISC_MSR 0x043b
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#define IA32_MC15_CTL_MSR 0x043c
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#define IA32_MC15_STATUS_MSR 0x043d
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#define IA32_MC15_ADDR_MSR 0x043e
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#define IA32_MC15_MISC_MSR 0x043f
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#define IA32_MC16_CTL_MSR 0x0440
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#define IA32_MC16_STATUS_MSR 0x0441
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#define IA32_MC16_ADDR_MSR 0x0442
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#define IA32_MC16_MISC_MSR 0x0443
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#define IA32_MC17_CTL_MSR 0x0444
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#define IA32_MC17_STATUS_MSR 0x0445
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#define IA32_MC17_ADDR_MSR 0x0446
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#define IA32_MC17_MISC_MSR 0x0447
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#define IA32_MC18_CTL_MSR 0x0448
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#define IA32_MC18_STATUS_MSR 0x0449
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#define IA32_MC18_ADDR_MSR 0x044a
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#define IA32_MC18_MISC_MSR 0x044b
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#define IA32_MC19_CTL_MSR 0x044c
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#define IA32_MC19_STATUS_MSR 0x044d
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#define IA32_MC19_ADDR_MSR 0x044e
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#define IA32_MC19_MISC_MSR 0x044f
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#define IA32_MC20_CTL_MSR 0x0450
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#define IA32_MC20_STATUS_MSR 0x0451
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#define IA32_MC20_ADDR_MSR 0x0452
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#define IA32_MC20_MISC_MSR 0x0453
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#define IA32_MC21_CTL_MSR 0x0454
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#define IA32_MC21_STATUS_MSR 0x0455
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#define IA32_MC21_ADDR_MSR 0x0456
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#define IA32_MC21_MISC_MSR 0x0457
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#define IA32_VMX_BASIC_MSR 0x0480
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#define IA32_VMX_PINBASED_CTLS_MSR 0x0481
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#define IA32_VMX_PROCBASED_CTLS_MSR 0x0482
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#define IA32_VMX_EXIT_CTLS_MSR 0x0483
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#define IA32_VMX_ENTRY_CTLS_MSR 0x0484
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#define IA32_VMX_MISC_MSR 0x0485
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#define IA32_VMX_CRO_FIXED0_MSR 0x0486
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#define IA32_VMX_CRO_FIXED1_MSR 0x0487
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#define IA32_VMX_CR4_FIXED0_MSR 0x0488
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#define IA32_VMX_CR4_FIXED1_MSR 0x0489
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#define IA32_VMX_VMCS_ENUM_MSR 0x048a
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#define IA32_VMX_PROCBASED_CTLS2_MSR 0x048b
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#define IA32_VMX_EPT_VPID_CAP_MSR 0x048c
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#define IA32_VMX_TRUE_PINBASED_CTLS_MSR 0x048d
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#define IA32_VMX_TRUE_PROCBASED_CTLS_MSR 0x048e
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#define IA32_VMX_TRUE_EXIT_CTLS_MSR 0x048f
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#define IA32_VMX_TRUE_ENTRY_CTLS_MSR 0x0490
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#define IA32_DS_AREA_MSR 0x0600
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#define IA32_EXT_XAPICID_MSR 0x0802
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#define IA32_EXT_XAPIC_VERSION_MSR 0x0803
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#define A32_EXT_XAPIC_TPR_MSR 0x0808
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#define IA32_EXT_XAPIC_PPR_MSR 0x080a
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#define IA32_EXT_XAPIC_EOI_MSR 0x080d
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#define IA32_EXT_XAPIC_LDR_MSR 0x080c
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#define IA32_EXT_XAPIC_SIVR_MSR 0x080f
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#define IA32_EXT_XAPIC_ISR0_MSR 0x0810
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#define IA32_EXT_XAPIC_ISR1_MSR 0x0811
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#define A32_EXT_XAPIC_ISR2_MSR 0x0812
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#define IA32_EXT_XAPIC_ISR3_MSR 0x0813
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#define IA32_EXT_XAPIC_ISR4_MSR 0x0814
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#define IA32_EXT_XAPIC_ISR5_MSR 0x0815
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#define IA32_EXT_XAPIC_ISR6_MSR 0x0816
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#define IA32_EXT_XAPIC_ISR7_MSR 0x0817
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#define IA32_EXT_XAPIC_TMR0_MSR 0x0818
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#define IA32_EXT_XAPIC_TMR1_MSR 0x0819
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#define IA32_EXT_XAPIC_TMR2_MSR 0x081a
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#define IA32_EXT_XAPIC_TMR3_MSR 0x081b
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#define IA32_EXT_XAPIC_TMR4_MSR 0x081c
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#define IA32_EXT_XAPIC_TMR5_MSR 0x081d
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#define IA32_EXT_XAPIC_TMR6_MSR 0x081e
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#define IA32_EXT_XAPIC_TMR7_MSR 0x081f
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#define IA32_EXT_XAPIC_IRR0_MSR 0x0820
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#define IA32_EXT_XAPIC_IRR1_MSR 0x0821
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#define IA32_EXT_XAPIC_IRR2_MSR 0x0822
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#define IA32_EXT_XAPIC_IRR3_MSR 0x0823
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#define IA32_EXT_XAPIC_IRR4_MSR 0x0824
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#define IA32_EXT_XAPIC_IRR5_MSR 0x0825
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#define IA32_EXT_XAPIC_IRR6_MSR 0x0826
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#define IA32_EXT_XAPIC_IRR7_MSR 0x0827
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#define IA32_EXT_XAPIC_ESR_MSR 0x0828
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#define IA32_EXT_XAPIC_LVT_CMCI_MSR 0x082f
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#define IA32_EXT_XAPIC_ICR_MSR 0x0830
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#define IA32_EXT_XAPIC_LVT_TIMER_MSR 0x0832
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#define IA32_EXT_XAPIC_LVT_THERMAL_MSR 0x0833
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#define IA32_EXT_XAPIC_LVT_PMI_MSR 0x0834
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#define IA32_EXT_XAPIC_LVT_LINT0_MSR 0x0835
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#define IA32_EXT_XAPIC_LVT_LINT1_MSR 0x0836
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#define IA32_EXT_XAPIC_LVT_ERROR_MSR 0x0837
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#define IA32_EXT_XAPIC_INIT_COUNT_MSR 0x0838
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#define IA32_EXT_XAPIC_CUR_COUNT_MSR 0x0839
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#define IA32_EXT_XAPIC_DIV_CONF_MSR 0x083e
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#define IA32_EXT_XAPIC_SELF_IPI_MSR 0x083f
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#define IA32_EFER_MSR 0xc0000080
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#define IA32_STAR_MSR 0xc0000081
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#define IA32_LSTAR_MSR 0xc0000082
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#define IA32_FMASK_MSR 0xc0000084
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#define IA32_FS_BASE_MSR 0xc0000100
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#define IA32_GS_BASE_MSR 0xc0000101
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#define IA32_KERNEL_GS_BASE_MSR 0xc0000102
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#define IA32_TSC_AUX_MSR 0xc0000103
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|
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/*
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* EFLAGS value to utilize for the initial context:
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*
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* IF (Interrupt Enable Flag) = 1
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* IOPL bits = 0
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* All other "flags" = Don't change state
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*/
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|
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#define EFLAGS_INITIAL 0x00000200
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#define EFLAGS_MASK 0x00003200
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|
|
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/* Enable paging and write protection */
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#define CR0_PAGING_ENABLE 0x80010000
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/* Clear the 5th bit in CR4 */
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#define CR4_PAE_DISABLE 0xFFFFFFEF
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/* Set the 5th bit in CR4 */
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#define CR4_PAE_ENABLE 0x00000020
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|
|
|
#ifndef _ASMLANGUAGE
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|
|
|
#include <misc/util.h>
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|
|
|
#ifdef DEBUG
|
|
#include <misc/printk.h>
|
|
#define PRINTK(...) printk(__VA_ARGS__)
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|
#else
|
|
#define PRINTK(...)
|
|
#endif /* DEBUG */
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
|
|
struct _kernel_arch {
|
|
#if defined(CONFIG_DEBUG_INFO)
|
|
NANO_ISF *isf; /* ptr to interrupt stack frame */
|
|
#endif
|
|
};
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|
|
|
typedef struct _kernel_arch _kernel_arch_t;
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _ASMLANGUAGE */
|
|
|
|
#endif /* _kernel_arch_data__h_ */
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