bf53ebf2c8
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types. There are few places we dont convert over to the new
types because of compatiability with ext/HALs or for ease of transition
at this point. Fixup a few of the PRI formatters so we build with newlib.
Jira: ZEP-2051
Change-Id: I7d2d3697cad04f20aaa8f6e77228f502cd9c8286
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
60 lines
1.1 KiB
C
60 lines
1.1 KiB
C
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Cache helper functions and defines (ARC)
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*
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* This file contains cache related functions and definitions for the
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* ARCv2 processor architecture.
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*/
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#ifndef _ARCV2_CACHE__H_
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#define _ARCV2_CACHE__H_
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#include <arch/cpu.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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/* i-cache defines for IC_CTRL register */
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#define IC_CACHE_ENABLE 0x00
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#define IC_CACHE_DISABLE 0x01
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#define IC_CACHE_DIRECT 0x00
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#define IC_CACHE_INDIRECT 0x20
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/*
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* @brief Initialize the I-cache
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*
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* Enables the i-cache and sets it to direct access mode.
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*/
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static ALWAYS_INLINE void _icache_setup(void)
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{
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u32_t icache_config = (
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IC_CACHE_DIRECT | /* direct mapping (one-way assoc.) */
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IC_CACHE_ENABLE /* i-cache enabled */
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);
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u32_t val;
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val = _arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
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val &= 0xff;
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if (val != 0) { /* is i-cache present? */
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/* configure i-cache */
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_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, icache_config);
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}
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}
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ARCV2_CACHE__H_ */
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