2a9b9b74bc
Zephyr does not currently allow deviation from standard terminology for a technology even if it is non-inclusive, until the corresponding standards body has confirmed intent to change that terminology. The terms used in a previous attempt to be inclusive do not match the expected forthcoming standard terms. Revert to standard terms until the new ones have been announced and the switch made throughout Zephyr. Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
42 lines
1.8 KiB
Plaintext
42 lines
1.8 KiB
Plaintext
I2C Slave API test
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##################
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.. note:
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See :ref:`coding_guideline_inclusive_language` for information about
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plans to change the terminology used in this API.
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This test verifies I2C slave driver implementations using two I2C
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controllers on a common bus. The test is supported by a test-specific
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driver that simulates an EEPROM with an I2C bus slave interface. Data
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is pre-loaded into the simulated devices outside the I2C API, and the
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Zephyr application issues commands to one controller that are responded
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to by the simulated EEPROM connected through the other controller.
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This test was originally designed for I2C controllers that support both
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master and slave behavior simultaneously. This is not true of all
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I2C controllers, so this behavior is now opt-in using
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CONFIG_APP_DUAL_ROLE_I2C. However, the devicetree still must provide a
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second EEPROM just to identify the bus.
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In slightly more detail the test has these phases:
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* Use API specific to the simulated EEPROM to pre-populate the simulated
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devices with device-specific content.
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* Register a simulated EEPROM as a I2C slave device on a bus. If
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CONFIG_APP_DUAL_ROLE_I2C is selected, register both.
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* Issue commands on one bus controller (operating as the bus master) and
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verify that the data supplied by the other controller (slave) match
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the expected values given the content known to be present on the
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simulated device. If CONFIG_APP_DUAL_ROLE_I2C is selected, do this
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with the roles reversed.
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Transfer of commands from one bus controller to the other is
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accomplished by hardware through having the SCL (and SDA) signals
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shorted to join the two buses.
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Presence of this required hardware configuration is identified by the
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`i2c_bus_short` fixture. If the buses are not connected as required,
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or the controller driver has bugs, the test will fail one or more I2C
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transactions.
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