5e4e0298e9
We assume that all x86 CPUs do have clflush instructions. And the cache line size is now provided through DTS. So detecting clflush instruction as well as the cache line size is no longer required at runtime and thus removed. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
26 lines
398 B
Plaintext
26 lines
398 B
Plaintext
# ATOM SoC configuration options
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_ATOM
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config SOC
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default "atom"
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 25000000 if HPET_TIMER
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if BT_UART
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config UART_PIPE_ON_DEV_NAME
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default "UART_1"
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depends on UART_PIPE
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config BT_MONITOR_ON_DEV_NAME
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default "UART_1" if BT_DEBUG_MONITOR
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endif
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endif
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