Tim Lin 309992280c soc: riscv: enable COMPRESSED_ISA for ITE chips ... Enable the config of COMPRESSED_ISA, this can work fine on 32-bit architecture. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>		2021-03-25 07:07:19 -04:00
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litex-vexriscv	soc: riscv: litex-vexriscv: change CSR accessors	2020-10-02 11:36:16 +02:00
openisa_rv32m1	riscv: add support for thread local storage	2020-10-24 10:52:00 -07:00
riscv-ite	soc: riscv: enable COMPRESSED_ISA for ITE chips	2021-03-25 07:07:19 -04:00
riscv-privilege	pinmux: sifive: Convert SiFive pinmux to be devicetree based	2021-02-15 08:33:00 -05:00
CMakeLists.txt	riscv32: rename to riscv	2019-08-02 13:54:48 -07:00