af67564573
Based upon discussions with HW designers the 32KHz
programming sequence can be simplified. When FW writes
a value to the VBAT 32KHz Clock Enable register HW checks
if the value is the same as the current value. If the same
the HW does nothing. If different HW begins a sequence to
switch off the current 32KHz source, revert to ring oscillator,
and switch to the new source. FW should program the new value
and then spin until the PCR OSC ID PLL Lock bit goes to 1.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
162 lines
3.9 KiB
C
162 lines
3.9 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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/*
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* Make sure PCR sleep enables are clear except for crypto
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* which do not have internal clock gating.
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*/
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static int soc_pcr_init(void)
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{
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PCR_REGS->SLP_EN0 = 0;
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PCR_REGS->SLP_EN1 = 0;
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PCR_REGS->SLP_EN2 = 0;
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PCR_REGS->SLP_EN4 = 0;
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PCR_REGS->SLP_EN3 = MCHP_PCR3_CRYPTO_MASK;
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return 0;
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}
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/*
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* Select 32KHz clock source used for PLL reference.
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* Options are:
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* Internal 32KHz silicon oscillator.
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* External parallel resonant crystal between XTAL1 and XTAL2 pins.
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* External single ended crystal connected to XTAL2 pin.
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* External 32KHz square wave from Host chipset/board on 32KHZ_IN pin.
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* NOTES:
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* FW Program new value to VBAT CLK32 Enable register.
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* HW if new value != current value
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* HW endif
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* FW spin until PCR PLL lock is set.
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* 32K stable and PLL locked.
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* PLL POR or clock source change can take up to 3ms to lock.
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* 32KHZ_IN pin must be configured for 32KHZ_IN function.
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* Crystals vary and may take longer time to stabilize this will
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* affect PLL lock time.
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* Crystal do not like to be power cycled. If using a crystal
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* the board should supply a battery backed (VBAT) power rail.
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* The VBAT clock control register selecting 32KHz source is
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* connected to the VBAT power rail. If using a battery one can
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* check the VBAT Power Fail and Reset Status register for a VBAT POR.
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*/
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static void clk32_change(uint8_t new_clk32)
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{
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/* Program new value. */
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VBATR_REGS->CLK32_EN = new_clk32 & MCHP_VBATR_CLKEN_MASK;
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/* Wait for PLL lock. HW state machine is configuring PLL. */
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while ((PCR_REGS->OSC_ID & MCHP_PCR_OSC_ID_PLL_LOCK) == 0)
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;
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}
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static int soc_clk32_init(void)
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{
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uint8_t new_clk32;
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#ifdef CONFIG_SOC_MEC1501_EXT_32K
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#ifdef CONFIG_SOC_MEC1501_EXT_32K_CRYSTAL
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#ifdef CONFIG_SOC_MEC1501_EXT_32K_PARALLEL_CRYSTAL
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new_clk32 = MCHP_VBATR_USE_PAR_CRYSTAL;
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#else
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new_clk32 = MCHP_VBATR_USE_SE_CRYSTAL;
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#endif
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#else
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/* Use 32KHZ_PIN as 32KHz source */
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new_clk32 = MCHP_VBATR_USE_32KIN_PIN;
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#endif
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#else
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/* Use internal 32KHz +/-2% silicon oscillator
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* if required performed OTP value override
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*/
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if (MCHP_DEVICE_ID() == 0x0020U) { /* MEC150x ? */
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if (MCHP_REVISION_ID() == MCHP_GCFG_REV_B0) {
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VBATR_REGS->CKK32_TRIM = 0x06U;
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}
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}
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new_clk32 = MCHP_VBATR_USE_SIL_OSC;
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#endif
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clk32_change(new_clk32);
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return 0;
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}
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/*
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* Initialize MEC1501 EC Interrupt Aggregator (ECIA) and external NVIC
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* inputs.
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*/
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static int soc_ecia_init(void)
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{
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GIRQ_Type *pg;
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uint32_t n;
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mchp_pcr_periph_slp_ctrl(PCR_ECIA, MCHP_PCR_SLEEP_DIS);
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ECS_REGS->INTR_CTRL |= MCHP_ECS_ICTRL_DIRECT_EN;
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/* gate off all aggregated outputs */
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ECIA_REGS->BLK_EN_CLR = 0xFFFFFFFFul;
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/* gate on GIRQ's that are aggregated only */
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ECIA_REGS->BLK_EN_SET = MCHP_ECIA_AGGR_BITMAP;
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/* Clear all GIRQn source enables and source status */
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pg = &ECIA_REGS->GIRQ08;
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for (n = MCHP_FIRST_GIRQ; n <= MCHP_LAST_GIRQ; n++) {
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pg->EN_CLR = 0xFFFFFFFFul;
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pg->SRC = 0xFFFFFFFFul;
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pg++;
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}
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/* Clear all external NVIC enables and pending status */
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for (n = 0u; n < MCHP_NUM_NVIC_REGS; n++) {
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NVIC->ICER[n] = 0xFFFFFFFFul;
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NVIC->ICPR[n] = 0xFFFFFFFFul;
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}
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return 0;
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}
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static int soc_init(const struct device *dev)
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{
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uint32_t isave;
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ARG_UNUSED(dev);
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isave = __get_PRIMASK();
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__disable_irq();
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soc_pcr_init();
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soc_clk32_init();
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/*
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* On HW reset PCR Processor Clock Divider = 4 for 48/4 = 12 MHz.
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* Set clock divider = 1 for maximum speed.
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* NOTE1: This clock divider affects all Cortex-M4 core clocks.
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* If you change it you must repogram SYSTICK to maintain the
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* same absolute time interval.
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*/
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PCR_REGS->PROC_CLK_CTRL = CONFIG_SOC_MEC1501_PROC_CLK_DIV;
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soc_ecia_init();
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if (!isave) {
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__enable_irq();
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}
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return 0;
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}
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SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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