zephyr/dts/bindings/interrupt-controller/riscv,plic0.yaml
Katsuhiro Suzuki 32f23059a2 dts: bindings: add IRQ priority support for SiFive PLIC
This patch adds IRQ priority support for SiFive PLIC by device-tree.
Some IRQ sources of plic use Kconfig to set priority of their IRQ.

- AON: no driver
- I2C, SPI, PWM: not use IRQ
- GPIO, UART: default 1

So this patch specifies IRQ priority 1 for all sources.

Currently these drivers (gpio and uart) do not support that they get
and use IRQ priority from device-tree. We need more patches.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-01-14 12:43:58 -06:00

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YAML

# Copyright (c) 2018, SiFive Inc.
# SPDX-License-Identifier: Apache-2.0
# Common fields for the RISC-V platform-local interrupt controller
include: [interrupt-controller.yaml, base.yaml]
properties:
reg:
required: true
riscv,max-priority:
type: int
description: maximum interrupt priority
required: true
"#interrupt-cells":
const: 2
interrupt-cells:
- irq
- priority