44cf206c2e
This maps devicetree GPIO phandle arrays from the full controller pin range to the sub-controllers required by Zephyr's limit of 32 pins per controller device. Signed-off-by: Peter A. Bigot <pab@pabigot.com>
23 lines
745 B
YAML
23 lines
745 B
YAML
# Copyright (c) 2019 Peter Bigot Consulting, LLC
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Apollo Lake GPIO Map
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Map from Apollo Lake GPIO to component GPIO driver instances.
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The Apollo Lake GPIO architecture provides four controllers each of
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which has more than 32 pins. To be supported on Zephyr these pins
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must be mapped to sub-devices that have no more than 32 pins each.
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This compatible is used to map the full controller to its
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subdevices.
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The NORTH controller supports 78 pins.
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The NORTHWEST controller supports 77 pins.
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The WEST controller supports 47 pins.
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The SOUTHWEST controller supports 43 pins.
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compatible: "intel,apollo-lake-gpio"
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include: [gpio-nexus.yaml, base.yaml]
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