716397411b
This commit fixes the incorrect memory (FLASH and SRAM) size specification in the device tree and the board test yaml files. The `qemu_cortex_r5` board (using `fdt-single_arch-zcu102-arm.dtb` FDT) has 64MiB RAM at the address 0 and 32MiB QSPI flash at 0xc0000000. QEMU `info mtree`: 0000000000000000-ffffffffffffffff (prio 0, i/o): memory@00000000 0000000000000000-000000000002ffff (prio 0, ram): ddr_bank1_1@0x0 0000000000030000-000000000003ffff (prio 0, ram): ddr_bank1_2@0x30000 0000000000040000-0000000003ffffff (prio 0, ram): ddr_bank1_3@0x40000 00000000c0000000-00000000c1ffffff (prio 0, i/o): lqspi Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
90 lines
2.1 KiB
Plaintext
90 lines
2.1 KiB
Plaintext
/*
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* Copyright (c) 2019 Lexmark International, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv7-r.dtsi>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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soc {
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flash0: flash@c0000000 {
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compatible = "soc-nv-flash";
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reg = <0xc0000000 DT_SIZE_M(32)>;
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};
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sram0: memory@0 {
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compatible = "mmio-sram";
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reg = <0 DT_SIZE_M(64)>;
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};
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uart0: uart@ff000000 {
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compatible = "xlnx,xuartps";
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reg = <0xff000000 0x4c>;
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status = "disabled";
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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label = "UART_0";
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};
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ttc0: timer@ff110000 {
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compatible = "xlnx,ttcps";
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status = "disabled";
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1", "irq_2";
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reg = <0xff110000 0x1000>;
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label = "ttc0";
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};
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ttc1: timer@ff120000 {
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compatible = "xlnx,ttcps";
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status = "disabled";
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1", "irq_2";
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reg = <0xff120000 0x1000>;
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label = "ttc1";
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};
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ttc2: timer@ff130000 {
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compatible = "xlnx,ttcps";
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status = "disabled";
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1", "irq_2";
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reg = <0xff130000 0x1000>;
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label = "ttc2";
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};
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ttc3: timer@ff140000 {
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compatible = "xlnx,ttcps";
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status = "disabled";
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1", "irq_2";
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reg = <0xff140000 0x1000>;
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label = "ttc3";
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};
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};
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};
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