38cd37f726
For memory that is truly device_type = "memory" we should not have a mmio-sram compatible. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
58 lines
1014 B
Plaintext
58 lines
1014 B
Plaintext
/* SPDX-License-Identifier: Apache-2.0 */
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/*
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* Copyright 2018 Broadcom.
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*/
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#include <arm/armv7-m.dtsi>
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#include <broadcom/valkyrie-irq.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m7";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv7m-mpu";
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reg = <0xe000ed90 0x40>;
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arm,num-mpu-regions = <16>;
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};
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};
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};
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soc {
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sram0: memory@400000 {
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device_type = "memory";
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reg = <0x00400000 0x30000>;
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};
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uart0: uart@40020000 {
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compatible = "ns16550";
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reg = <0x40020000 0x400>;
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clock-frequency = <25000000>;
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interrupts = <MCU_AON_UART_INTR 3>;
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label = "UART_0";
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status = "disabled";
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};
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uart1: uart@48100000 {
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compatible = "ns16550";
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reg = <0x48100000 0x400>;
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clock-frequency = <100000000>;
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interrupts = <UART0_INTR 3>;
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label = "UART_1";
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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