b0bd5a6ece
Introduces a new flash driver for the FlexSPI peripheral on i.MX RT SoCs. The hardware provides a flexible sequence engine (LUT) that supports various types of external devices, including serial NOR flash, serial NAND flash, HyperBus (HyperFlash/HyperRAM), and FPGAs. It supports up to four connected devices in single/dual/quad/octal modes and provides memory-mapped read/write access to these devices through the AHB bus. The driver implementation consists of a shared controller for each FlexSPI peripheral instance, and protocol-specific device drivers for each external device. The controller provides a private interface for multiple devices to access the FlexSPI peripheral registers. FlexSPI devices provide the public flash driver interface to applications or subsystems like storage or flash file systems; they also provide protocol-specific LUT sequences to the controller. Currently the only device type supported is QSPI NOR flash, but other types like HyperFlash will be added later. XIP is not yet supported, as this requires additional work to relocate code to RAM and managing interrupts. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
24 lines
610 B
C
24 lines
610 B
C
/*
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* Copyright 2020 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/flash.h>
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#include <fsl_flexspi.h>
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int flash_flexspi_update_lut(const struct device *dev, uint32_t index,
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const uint32_t *cmd, uint32_t count);
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int flash_flexspi_set_flash_config(const struct device *dev,
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const flexspi_device_config_t *device_config,
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flexspi_port_t port);
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int flash_flexspi_reset(const struct device *dev);
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int flash_flexspi_transfer(const struct device *dev,
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flexspi_transfer_t *transfer);
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void *flash_flexspi_get_ahb_address(const struct device *dev,
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flexspi_port_t port, off_t offset);
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