Andy Ross ae4f7a1a06 arch/xtensa: Remember to spill windows in arch_cohere_stacks() ... When we reach this code in interrupt context, our upper GPRs contain a cross-stack call that may still include some registers from the interrupted thread. Those need to go out to memory before we can do our cache coherence dance here. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>		2021-03-08 11:14:27 -05:00
..
include	arch: xtensa: Print backtrace from panic handler	2021-01-23 08:43:10 -05:00
offsets	arch/xtensa: General cleanup, remove dead code	2021-03-08 11:14:27 -05:00
startup	license: add missing SPDX headers	2021-02-11 08:05:16 -05:00
CMakeLists.txt	arch/xtensa: Inline atomics	2021-03-08 11:14:27 -05:00
cpu_idle.c	tracing: move headers under include/tracing	2020-02-07 15:58:05 -05:00
crt1.S	arch/xtensa: soc/intel_adsp: Rework MP code entry	2021-03-08 11:14:27 -05:00
debug_helpers_asm.S	arch: xtensa: Print backtrace from panic handler	2021-01-23 08:43:10 -05:00
fatal.c	arch/xtensa: General cleanup, remove dead code	2021-03-08 11:14:27 -05:00
irq_manage.c	arch/xtensa: General cleanup, remove dead code	2021-03-08 11:14:27 -05:00
irq_offload.c	arch/xtensa: General cleanup, remove dead code	2021-03-08 11:14:27 -05:00
README-WINDOWS.rst	arch/xtensa: Add an arch-internal README on register windows	2021-03-08 11:14:27 -05:00
tls.c	xtensa: add support for thread local storage	2020-10-24 10:52:00 -07:00
window_vectors.S	arch/xtensa: General cleanup, remove dead code	2021-03-08 11:14:27 -05:00
xtensa_backtrace.c	arch: xtensa: Print backtrace from panic handler	2021-01-23 08:43:10 -05:00
xtensa_intgen.tmpl	xtensa: Interrupt generator script and output for qemu & esp32	2018-02-16 10:44:29 -05:00
xtensa-asm2-util.S	arch/xtensa: Remember to spill windows in arch_cohere_stacks()	2021-03-08 11:14:27 -05:00
xtensa-asm2.c	arch/xtensa: Invalidate bottom of outbound stacks	2021-03-08 11:14:27 -05:00