07160fa153
SPARC is an open and royalty free processor architecture. This commit provides SPARC architecture support to Zephyr. It is compatible with the SPARC V8 specification and the SPARC ABI and is independent of processor implementation. Functionality specific to SPRAC processor implementations should go in soc/sparc. One example is the LEON3 SOC which is part of this patch set. The architecture port is fully SPARC ABI compatible, including trap handlers and interrupt context. Number of implemented register windows can be configured. Some SPARC V8 processors borrow the CASA (compare-and-swap) atomic instructions from SPARC V9. An option has been defined in the architecture port to forward the corresponding code-generation option to the compiler. Stack size related config options have been defined in sparc/Kconfig to match the SPARC ABI. Co-authored-by: Nikolaus Huber <nikolaus.huber.melk@gmail.com> Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
70 lines
2.1 KiB
C
70 lines
2.1 KiB
C
/*
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* Copyright (c) 2019-2020 Cobham Gaisler AB
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_ARCH_SPARC_INCLUDE_OFFSETS_SHORT_ARCH_H_
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#define ZEPHYR_ARCH_SPARC_INCLUDE_OFFSETS_SHORT_ARCH_H_
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#include <offsets.h>
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#define _thread_offset_to_y \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_y_OFFSET)
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#define _thread_offset_to_l0_and_l1 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_l0_and_l1_OFFSET)
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#define _thread_offset_to_l2 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_l2_OFFSET)
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#define _thread_offset_to_l3 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_l3_OFFSET)
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#define _thread_offset_to_l4 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_l4_OFFSET)
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#define _thread_offset_to_l5 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_l5_OFFSET)
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#define _thread_offset_to_l6 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_l6_OFFSET)
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#define _thread_offset_to_l7 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_l7_OFFSET)
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#define _thread_offset_to_i0 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_i0_OFFSET)
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#define _thread_offset_to_i1 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_i1_OFFSET)
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#define _thread_offset_to_i2 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_i2_OFFSET)
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#define _thread_offset_to_i3 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_i3_OFFSET)
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#define _thread_offset_to_i4 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_i4_OFFSET)
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#define _thread_offset_to_i5 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_i5_OFFSET)
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#define _thread_offset_to_i6 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_i6_OFFSET)
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#define _thread_offset_to_i7 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_i7_OFFSET)
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#define _thread_offset_to_o6 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_o6_OFFSET)
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#define _thread_offset_to_o7 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_o7_OFFSET)
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#define _thread_offset_to_psr \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_psr_OFFSET)
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#endif /* ZEPHYR_ARCH_SPARC_INCLUDE_OFFSETS_SHORT_ARCH_H_ */
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