53a4acb2dc
This change adds full shared floating point support for the SPARC architecture. All SPARC floating point registers are scratch registers with respect to function call boundaries. That means we only have to save floating point registers when switching threads in ISR. The registers are stored to the corresponding thread stack. FPU is disabled when calling ISR. Any attempt to use FPU in ISR will generate the fp_disabled trap which causes Zephyr fatal error. - This commit adds no new thread state. - All FPU contest save/restore is synchronous and lazy FPU context switch is not implemented. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
331 lines
7.6 KiB
ArmAsm
331 lines
7.6 KiB
ArmAsm
/*
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* Copyright (c) 2019-2020 Cobham Gaisler AB
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <offsets_short.h>
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#include <arch/sparc/sparc.h>
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#include "stack_offsets.h"
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GTEXT(__sparc_trap_interrupt)
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GTEXT(__sparc_trap_irq_offload)
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/*
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* Interrupt trap handler
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*
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* - IU state is saved and restored
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*
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* On entry:
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* %l0: psr (set by trap code)
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* %l1: pc
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* %l2: npc
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* %l3: SPARC interrupt request level (bp_IRL)
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* %fp: %sp of current register window at trap time
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*
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* This module also implements the IRQ offload support. The handling is the
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* same as for asynchronous maskable interrupts, with the following exceptions:
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* - Do not re-execute the causing (ta) instruction at trap exit.
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* - A dedicated interrupt request level (0x8d) is used.
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* - z_sparc_enter_irq() knows how to interpret this interrupt request level.
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*/
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SECTION_SUBSEC_FUNC(TEXT, __sparc_trap_interrupt, __sparc_trap_irq_offload)
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/* Preparation in the case of synchronous IRQ offload. */
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mov %l2, %l1
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add %l2, 4, %l2
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set 0x8d, %l3
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__sparc_trap_interrupt:
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/* %g2, %g3 are used at manual window overflow so save temporarily */
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mov %g2, %l4
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mov %g3, %l5
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/* We may have trapped into the invalid window. If so, make it valid. */
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rd %wim, %g2
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srl %g2, %l0, %g3
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cmp %g3, 1
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bne .Lwodone
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nop
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/* Do the window overflow. */
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sll %g2, (CONFIG_SPARC_NWIN-1), %g3
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srl %g2, 1, %g2
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or %g2, %g3, %g2
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/* Enter window to save. */
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save
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/* Install new wim calculated above. */
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mov %g2, %wim
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nop
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nop
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nop
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/* Put registers on the dedicated save area of the ABI stack frame. */
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std %l0, [%sp + 0x00]
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std %l2, [%sp + 0x08]
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std %l4, [%sp + 0x10]
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std %l6, [%sp + 0x18]
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std %i0, [%sp + 0x20]
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std %i2, [%sp + 0x28]
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std %i4, [%sp + 0x30]
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std %i6, [%sp + 0x38]
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/* Leave saved window. */
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restore
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.Lwodone:
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/*
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* %l4: %g2 at trap time
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* %l5: %g3 at trap time
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*
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* Save the state of the interrupted task including global registers on
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* the task stack.
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*
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* IMPORTANT: Globals are saved here as well on the task stack, since a
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* context switch might happen before the context of this interrupted
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* task is restored.
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*/
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/* Allocate stack for isr context. */
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sub %fp, ISF_SIZE, %sp
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/*
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* %fp: %sp of interrupted task
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* %sp: %sp of interrupted task - ISF_SIZE.
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* (fits what we store here)
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*
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* Save the interrupted context.
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*/
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std %l0, [%sp + ISF_PSR_OFFSET] /* psr pc */
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st %l2, [%sp + ISF_NPC_OFFSET] /* npc */
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st %g1, [%sp + ISF_G1_OFFSET] /* g1 */
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std %l4, [%sp + ISF_G2_OFFSET] /* g2 g3 */
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st %g4, [%sp + ISF_G4_OFFSET] /* g4 */
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rd %y, %g1
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st %g1, [%sp + ISF_Y_OFFSET] /* y */
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/* %l5: reference to _kernel */
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set _kernel, %l5
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/* Switch to interrupt stack. */
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mov %sp, %fp
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ld [%l5 + _kernel_offset_to_irq_stack], %sp
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/* Allocate a full C stack frame */
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sub %sp, STACK_FRAME_SIZE, %sp
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/*
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* %fp: %sp of interrupted task - ISF_SIZE.
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* %sp: irq stack - 96. An ABI frame
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*/
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/* Enable traps, raise PIL to mask all maskable interrupts. */
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or %l0, PSR_PIL, %l6
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#if defined(CONFIG_FPU)
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/*
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* We now check if the interrupted context was using the FPU. The
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* result is stored in register l5 which will either get the value 0
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* (FPU not used) or PSR_EF (FPU used).
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*
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* If the FPU was used by the interrupted context, then we do two
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* things:
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* 1. Store FSR to memory. This has the side-effect of completing all
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* pending FPU operations.
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* 2. Disable FPU. Floating point instructions in the ISR will trap.
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*
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* The FPU is be enabled again if needed after the ISR has returned.
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*/
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set PSR_EF, %l5
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andcc %l0, %l5, %l5
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bne,a 1f
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st %fsr, [%sp]
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1:
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andn %l6, %l5, %l6
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#endif
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wr %l6, PSR_ET, %psr
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nop
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nop
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nop
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#ifdef CONFIG_TRACING_ISR
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call sys_trace_isr_enter
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nop
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#endif
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/* SPARC interrupt request level is the first argument */
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call z_sparc_enter_irq
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mov %l3, %o0
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#ifdef CONFIG_TRACING_ISR
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call sys_trace_isr_exit
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nop
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#endif
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/*
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* %fp: %sp of interrupted task - ISF_SIZE.
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* %sp: irq stack - 96. An ABI frame
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*/
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#ifdef CONFIG_PREEMPT_ENABLED
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/* allocate stack for calling C function and for its output value */
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sub %fp, (96+8), %sp
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/*
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* %fp: %sp of interrupted task - ISF_SIZE.
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* %sp: %sp of interrupted task - ISF_SIZE - STACK_FRAME_SIZE - 8.
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*/
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call z_arch_get_next_switch_handle
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add %sp, 96, %o0
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/* we get old thread as "return value" on stack */
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ld [%sp + 96], %o1
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/*
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* o0: new thread
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* o1: old thread
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*/
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cmp %o0, %o1
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beq .Lno_reschedule
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/* z_sparc_context_switch() is a leaf function not using stack. */
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add %sp, (96+8-64), %sp
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#if defined(CONFIG_FPU_SHARING)
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/* IF PSR_EF at trap time then store the FP context. */
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cmp %l5, 0
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be .Lno_fp_context
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nop
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/*
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* PSR_EF was 1 at trap time so save the FP registers on stack.
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* - Set PSR_EF so we can access the FP registers.
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* - Allocate space for the FP registers above the save area used for
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* the z_sparc_context_switch() call.
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*/
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wr %l6, %l5, %psr
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nop
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nop
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nop
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sub %sp, 34 * 4, %sp
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std %f0, [%sp + 64 + 0x00]
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std %f2, [%sp + 64 + 0x08]
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std %f4, [%sp + 64 + 0x10]
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std %f6, [%sp + 64 + 0x18]
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std %f8, [%sp + 64 + 0x20]
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std %f10, [%sp + 64 + 0x28]
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std %f12, [%sp + 64 + 0x30]
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std %f14, [%sp + 64 + 0x38]
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std %f16, [%sp + 64 + 0x40]
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std %f18, [%sp + 64 + 0x48]
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std %f20, [%sp + 64 + 0x50]
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std %f22, [%sp + 64 + 0x58]
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std %f24, [%sp + 64 + 0x60]
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std %f26, [%sp + 64 + 0x68]
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std %f28, [%sp + 64 + 0x70]
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std %f30, [%sp + 64 + 0x78]
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call z_sparc_context_switch
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st %fsr, [%sp + 64 + 0x80]
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ldd [%sp + 64 + 0x00], %f0
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ldd [%sp + 64 + 0x08], %f2
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ldd [%sp + 64 + 0x10], %f4
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ldd [%sp + 64 + 0x18], %f6
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ldd [%sp + 64 + 0x20], %f8
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ldd [%sp + 64 + 0x28], %f10
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ldd [%sp + 64 + 0x30], %f12
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ldd [%sp + 64 + 0x38], %f14
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ldd [%sp + 64 + 0x40], %f16
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ldd [%sp + 64 + 0x48], %f18
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ldd [%sp + 64 + 0x50], %f20
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ldd [%sp + 64 + 0x58], %f22
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ldd [%sp + 64 + 0x60], %f24
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ldd [%sp + 64 + 0x68], %f26
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ldd [%sp + 64 + 0x70], %f28
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ldd [%sp + 64 + 0x78], %f30
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ld [%sp + 64 + 0x80], %fsr
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ba .Lno_reschedule
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add %sp, 34 * 4, %sp
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.Lno_fp_context:
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#endif /* CONFIG_FPU_SHARING */
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call z_sparc_context_switch
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nop
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.Lno_reschedule:
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#endif /* CONFIG_PREEMPT_ENABLED */
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/* Restore the interrupted context. */
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ld [%fp + ISF_Y_OFFSET], %g1
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wr %g1, 0, %y
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ldd [%fp + ISF_PSR_OFFSET], %l0 /* psr, pc */
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ld [%fp + ISF_NPC_OFFSET], %l2 /* npc */
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/* NOTE: %g1 will be restored later */
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/* %g1 is used to access the stack frame later */
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mov %fp, %g1
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ldd [%fp + ISF_G2_OFFSET], %g2
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ld [%fp + ISF_G4_OFFSET], %g4
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add %fp, ISF_SIZE, %fp
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/*
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* Install the PSR we got from the interrupt context. Current PSR.CWP
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* is preserved. Keep PSR.ET=0 until we do "rett".
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*/
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rd %psr, %l3
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and %l3, PSR_CWP, %l3
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andn %l0, (PSR_CWP | PSR_ET), %l0
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or %l3, %l0, %l0
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mov %l0, %psr
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nop
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nop
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nop
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/* Calculate %l6 := (cwp+1) % NWIN */
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rd %wim, %l3
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set (CONFIG_SPARC_NWIN), %l7
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add %l0, 1, %l6
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and %l6, PSR_CWP, %l6
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cmp %l6, %l7
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bge,a .Lwrapok
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mov 0, %l6
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.Lwrapok:
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/* Determine if we must prepare the return window. */
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/* %l5 := %wim >> (cwp+1) */
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srl %l3, %l6, %l5
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/* %l5 is 1 if (cwp+1) is an invalid window */
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cmp %l5, 1
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bne .Lwudone
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sub %l7, 1, %l7 /* %l7 := NWIN - 1 */
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/* Do the window underflow. */
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sll %l3, 1, %l4
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srl %l3, %l7, %l5
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wr %l4, %l5, %wim
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nop
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nop
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nop
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restore
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ldd [%g1 + 0x00], %l0
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ldd [%g1 + 0x08], %l2
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ldd [%g1 + 0x10], %l4
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ldd [%g1 + 0x18], %l6
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ldd [%g1 + 0x20], %i0
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ldd [%g1 + 0x28], %i2
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ldd [%g1 + 0x30], %i4
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ldd [%g1 + 0x38], %i6
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save
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.Lwudone:
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/*
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* Restore %psr since we may have trashed condition codes. PSR.ET is
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* still 0.
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*/
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wr %l0, %psr
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nop
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nop
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nop
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/* restore g1 */
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ld [%g1 + ISF_G1_OFFSET], %g1
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jmp %l1
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rett %l2
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