3539c2fbb3
Split ARM and ARM64 architectures. Details: - CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore) - Arch and include AArch64 files are in a dedicated directory (arch/arm64 and include/arch/arm64) - AArch64 boards and SoC are moved to soc/arm64 and boards/arm64 - AArch64-specific DTS files are moved to dts/arm64 - The A72 support for the bcm_vk/viper board is moved in the boards/bcm_vk/viper directory Signed-off-by: Carlo Caione <ccaione@baylibre.com>
249 lines
6.6 KiB
ArmAsm
249 lines
6.6 KiB
ArmAsm
/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Populated vector table
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <arch/cpu.h>
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#include <offsets_short.h>
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#include "vector_table.h"
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_ASM_FILE_PROLOGUE
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/*
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* Save volatile registers, x30, SPSR_EL1 and ELR_EL1
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*
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* Save the volatile registers and x30 on the process stack. This is
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* needed if the thread is switched out because they can be clobbered by the
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* ISR and/or context switch.
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*/
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.macro z_arm64_enter_exc xreg0, xreg1
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/* Switch to SP_EL0 */
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msr spsel, #0
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/*
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* Two things can happen to the remaining registers:
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*
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* - No context-switch: in this case x19-x28 are callee-saved register
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* so we can be sure they are not going to be clobbered by ISR.
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* - Context-switch: the callee-saved registers are saved by
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* z_arm64_context_switch() in the kernel structure.
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*/
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sub sp, sp, ___esf_t_SIZEOF
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stp x0, x1, [sp, ___esf_t_x0_x1_OFFSET]
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stp x2, x3, [sp, ___esf_t_x2_x3_OFFSET]
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stp x4, x5, [sp, ___esf_t_x4_x5_OFFSET]
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stp x6, x7, [sp, ___esf_t_x6_x7_OFFSET]
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stp x8, x9, [sp, ___esf_t_x8_x9_OFFSET]
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stp x10, x11, [sp, ___esf_t_x10_x11_OFFSET]
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stp x12, x13, [sp, ___esf_t_x12_x13_OFFSET]
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stp x14, x15, [sp, ___esf_t_x14_x15_OFFSET]
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stp x16, x17, [sp, ___esf_t_x16_x17_OFFSET]
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stp x18, x30, [sp, ___esf_t_x18_x30_OFFSET]
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mrs \xreg0, spsr_el1
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mrs \xreg1, elr_el1
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stp \xreg0, \xreg1, [sp, ___esf_t_spsr_elr_OFFSET]
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#ifdef CONFIG_USERSPACE
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/* Save the current kernel/user mode in the context */
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mrs \xreg0, tpidrro_el0
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str \xreg0, [sp, ___esf_t_tpidrro_el0_OFFSET]
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/* Switch TPIDRRO_EL0 to kernel mode */
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msr tpidrro_el0, xzr
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#endif
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.endm
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/*
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* Four types of exceptions:
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* - synchronous: aborts from MMU, SP/CP alignment checking, unallocated
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* instructions, SVCs/SMCs/HVCs, ...)
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* - IRQ: group 1 (normal) interrupts
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* - FIQ: group 0 or secure interrupts
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* - SError: fatal system errors
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*
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* Four different contexts:
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* - from same exception level, when using the SP_EL0 stack pointer
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* - from same exception level, when using the SP_ELx stack pointer
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* - from lower exception level, when this is AArch64
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* - from lower exception level, when this is AArch32
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*
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* +------------------+------------------+-------------------------+
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* | Address | Exception type | Description |
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* +------------------+------------------+-------------------------+
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* | VBAR_ELn + 0x000 | Synchronous | Current EL with SP0 |
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* | + 0x080 | IRQ / vIRQ | |
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* | + 0x100 | FIQ / vFIQ | |
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* | + 0x180 | SError / vSError | |
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* +------------------+------------------+-------------------------+
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* | + 0x200 | Synchronous | Current EL with SPx |
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* | + 0x280 | IRQ / vIRQ | |
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* | + 0x300 | FIQ / vFIQ | |
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* | + 0x380 | SError / vSError | |
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* +------------------+------------------+-------------------------+
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* | + 0x400 | Synchronous | Lower EL using AArch64 |
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* | + 0x480 | IRQ / vIRQ | |
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* | + 0x500 | FIQ / vFIQ | |
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* | + 0x580 | SError / vSError | |
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* +------------------+------------------+-------------------------+
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* | + 0x600 | Synchronous | Lower EL using AArch32 |
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* | + 0x680 | IRQ / vIRQ | |
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* | + 0x700 | FIQ / vFIQ | |
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* | + 0x780 | SError / vSError | |
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* +------------------+------------------+-------------------------+
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*/
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/* The whole table must be 2K aligned */
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SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
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.align 11
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/* Current EL with SP0 / Synchronous */
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.align 7
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z_arm64_enter_exc x0, x1
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b z_arm64_sync_exc
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/* Current EL with SP0 / IRQ */
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.align 7
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z_arm64_enter_exc x0, x1
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#ifdef CONFIG_GEN_SW_ISR_TABLE
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b _isr_wrapper
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#else
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b z_irq_spurious
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#endif
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/* Current EL with SP0 / FIQ */
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.align 7
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b .
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/* Current EL with SP0 / SError */
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.align 7
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z_arm64_enter_exc x0, x1
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b z_arm64_serror
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/* Current EL with SPx / Synchronous */
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.align 7
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z_arm64_enter_exc x0, x1
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b z_arm64_sync_exc
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/* Current EL with SPx / IRQ */
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.align 7
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z_arm64_enter_exc x0, x1
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#ifdef CONFIG_GEN_SW_ISR_TABLE
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b _isr_wrapper
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#else
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b z_irq_spurious
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#endif
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/* Current EL with SPx / FIQ */
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.align 7
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b .
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/* Current EL with SPx / SError */
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.align 7
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z_arm64_enter_exc x0, x1
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b z_arm64_serror
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/* Lower EL using AArch64 / Synchronous */
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.align 7
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z_arm64_enter_exc x0, x1
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b z_arm64_sync_exc
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/* Lower EL using AArch64 / IRQ */
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.align 7
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z_arm64_enter_exc x0, x1
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#ifdef CONFIG_GEN_SW_ISR_TABLE
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b _isr_wrapper
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#else
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b z_irq_spurious
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#endif
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/* Lower EL using AArch64 / FIQ */
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.align 7
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b .
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/* Lower EL using AArch64 / SError */
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.align 7
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z_arm64_enter_exc x0, x1
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b z_arm64_serror
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/* Lower EL using AArch32 / Synchronous */
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.align 7
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b .
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/* Lower EL using AArch32 / IRQ */
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.align 7
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b .
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/* Lower EL using AArch32 / FIQ */
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.align 7
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b .
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/* Lower EL using AArch32 / SError */
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.align 7
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b .
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GTEXT(z_arm64_serror)
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SECTION_FUNC(TEXT, z_arm64_serror)
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mov x1, sp
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mov x0, #0 /* K_ERR_CPU_EXCEPTION */
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bl z_arm64_fatal_error
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/* Return here only in case of recoverable error */
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b z_arm64_exit_exc
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/*
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* Restore volatile registers, x30, SPSR_EL1 and ELR_EL1
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*
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* This is the common exit point for z_arm64_sync_exc() and _isr_wrapper().
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*/
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GTEXT(z_arm64_exit_exc)
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SECTION_FUNC(TEXT, z_arm64_exit_exc)
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ldp x0, x1, [sp, ___esf_t_spsr_elr_OFFSET]
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msr spsr_el1, x0
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msr elr_el1, x1
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#ifdef CONFIG_USERSPACE
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/* Restore the kernel/user mode flag */
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ldr x0, [sp, ___esf_t_tpidrro_el0_OFFSET]
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msr tpidrro_el0, x0
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#endif
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ldp x0, x1, [sp, ___esf_t_x0_x1_OFFSET]
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ldp x2, x3, [sp, ___esf_t_x2_x3_OFFSET]
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ldp x4, x5, [sp, ___esf_t_x4_x5_OFFSET]
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ldp x6, x7, [sp, ___esf_t_x6_x7_OFFSET]
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ldp x8, x9, [sp, ___esf_t_x8_x9_OFFSET]
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ldp x10, x11, [sp, ___esf_t_x10_x11_OFFSET]
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ldp x12, x13, [sp, ___esf_t_x12_x13_OFFSET]
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ldp x14, x15, [sp, ___esf_t_x14_x15_OFFSET]
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ldp x16, x17, [sp, ___esf_t_x16_x17_OFFSET]
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ldp x18, x30, [sp, ___esf_t_x18_x30_OFFSET]
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add sp, sp, ___esf_t_SIZEOF
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/*
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* In general in the ELR_EL1 register we can find:
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*
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* - The address of ret in z_arm64_call_svc()
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* - The address of the next instruction at the time of the IRQ when the
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* thread was switched out.
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* - The address of z_thread_entry() for new threads (see thread.c).
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*/
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eret
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