e128f3c5d9
This commit re-works the test for the ARM architecture, so that it can work with any available NVIC IRQ, not bound to use the last 2 NVIC lines. It makes use of the dynamic IRQ feature. Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
80 lines
1.6 KiB
C
80 lines
1.6 KiB
C
/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <ztest.h>
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#include <irq_offload.h>
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#include <kernel_structs.h>
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#if defined(CONFIG_ARM)
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#include <arch/arm/cortex_m/cmsis.h>
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static u32_t get_available_nvic_line(u32_t initial_offset)
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{
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int i;
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for (i = initial_offset - 1; i >= 0; i--) {
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if (NVIC_GetEnableIRQ(i) == 0) {
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/*
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* Interrupts configured statically with IRQ_CONNECT(.)
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* are automatically enabled. NVIC_GetEnableIRQ()
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* returning false, here, implies that the IRQ line is
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* either not implemented or it is not enabled, thus,
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* currently not in use by Zephyr.
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*/
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/* Set the NVIC line to pending. */
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NVIC_SetPendingIRQ(i);
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if (NVIC_GetPendingIRQ(i)) {
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/* If the NVIC line is pending, it is
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* guaranteed that it is implemented.
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*/
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break;
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}
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}
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}
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zassert_true(i >= 0, "No available IRQ line\n");
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return i;
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}
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static void trigger_irq(int irq)
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{
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printk("Triggering irq : %d\n", irq);
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#if defined(CONFIG_SOC_TI_LM3S6965_QEMU) || defined(CONFIG_CPU_CORTEX_M0) \
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|| defined(CONFIG_CPU_CORTEX_M0PLUS)
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NVIC_SetPendingIRQ(irq);
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#else
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NVIC->STIR = irq;
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#endif
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}
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#elif defined(CONFIG_RISCV)
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static void trigger_irq(int irq)
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{
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u32_t mip;
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printk("Triggering irq : %d\n", irq);
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__asm__ volatile ("csrrs %0, mip, %1\n"
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: "=r" (mip)
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: "r" (1 << irq));
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}
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#elif defined(CONFIG_CPU_ARCV2)
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static void trigger_irq(int irq)
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{
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printk("Triggering irq : %d\n", irq);
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z_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_HINT, irq);
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}
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#else
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/* for not supported architecture */
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#define NO_TRIGGER_FROM_SW
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#endif
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