43d1d15da8
There is some legacy code that tries to mask IDC interrupts when starting up cores. This is there because the IDC interrupt is both the system IPI when Zephyr is running (and can thus be signaled asynchronously to the code calling arch_start_cpu()) and the messaging protocol to the boot ROM on the other CPU. So the idea is that we mask interrupts after startup so nothing is confused. But that's needless in the current architecture. We maintain a synchronized cpus_active[] record that will show true/active for any CPU between the end of its SMP startup sequence and the beginning of the shutdown process in soc_halt_cpu(), and false at all other times. An IPI will never be sent to a CPU that is running in the boot ROM, because such a CPU will be flagged as inactive. Likewise a ROM startup IDC will never be sent to a CPU running Zephyr code for the converse reason. Remove all that code. Unfortunately SOF itself still needs an interrupt unmask step at CPU startup, because it's still doing its own masking (probably according to the same algorithm that we imported). Leave that in place as a minimal workaround until we get that fixed upstream. Signed-off-by: Andy Ross <andrew.j.ross@intel.com> |
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| .. | ||
| esp32 | ||
| esp32s2 | ||
| intel_adsp | ||
| intel_s1000 | ||
| nxp_adsp | ||
| sample_controller | ||
| CMakeLists.txt | ||